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LPC47S45x
Advanced I/O with X-Bus Interface
FEATURES
3.3 Volt Operation (5V tolerant) Floppy Disk Controller (Supports 2 FDCs) Multi-Mode Parallel Port Two UARTs 8042 Keyboard Controller SMBus Controller - SMBus access to LCD Interface - SMBus Serial Port 2 Interface Disable - SMBus access to Power On Elapsed Time Counters - Programmable Slave Address X-Bus Interface - Supports up to four external I/O components - Offers two modes of operation - Support for Driving LCD Panel Interface Controller - Supports Port 80h "Snooping" Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (55) Fan Controller - One Fan Speed Control Output - One Fan Tachometer Input ISA IRQ to Serial IRQ Conversion XNOR Chain for Board Test Mode PC2001 and ACPI 2.0 Compliant 128-pin QFP Package ISA Plug-and-Play Compatible Register Set Intelligent Auto Power Management Power On Elapsed Time Counters - Counter for Main Power - Counter for Standby Power Real Time Clock - MC146818 and DS1287 Compatible - 256 Bytes of Battery Backed CMOS in Two 128Byte Banks - 128 Bytes of CMOS RAM Lockable in 4x32 Byte Blocks - 12 and 24 Hour Time Format - 24-hour daily alarm - 30-day alarm - Binary and BCD Format - <1A Standby Current (typ)
SMSC LPC47S45x
2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format - 16-Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - 480 Address, up to 15 IRQ and Four DMA Options Enhanced Digital Data Separator - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Keyboard Controller - 8042 Software Compatible - 8-Bit Microcomputer - 2k Bytes of Program ROM - 256 Bytes of Data RAM - Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface - Asynchronous Access to Two Data Registers and One Status Register - Supports Interrupt and Polling Access - 8-Bit Counter Timer - Port 92 Support - Fast Gate A20 and KRESET Outputs Serial Ports - Two Full Function Serial Ports - High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry - 480 Address and 15 IRQ Options - IrDA 1.0, HP-SIR, ASK IR Support
Rev. 04-30-07
DATASHEET
Multi-Mode Parallel Port with ChiProtect - Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - IEEE 1284 Compliant Enhanced Capabilities Port (ECP) - ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 960 Address, up to 15 IRQ and Four DMA Options
Pin Reduced ISA Host Interface (LPC Bus) - Multiplexed Command, Address and Data Bus - 8-Bit I/O Transfers - 8-Bit DMA Transfers - 16-Bit Address Qualification - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - Power Management Event (PME) Interface Pin Power Management ACPI Registers
ORDERING INFORMATION
LPC47S457-NS for 128 pin QFP package with Phoenix 42i Keyboard BIOS Lead-Free RoHS Compliant) LPC47S457-NC for 128 pin QFP package with Phoenix 42i Keyboard BIOS
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC LPC47S45x Page 2 of 259 Rev. 04-30-07
DATASHEET
TABLE OF CONTENTS
1 2 3 4 GENERAL DESCRIPTION .................................................................................................................... 9 PIN CONFIGURATION ........................................................................................................................ 10 PINOUT ................................................................................................................................................ 11 PIN DESCRIPTION .............................................................................................................................. 12
4.1 4.2 BUFFER TYPE DESCRIPTIONS ............................................................................................................................17 PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS............................................................................................18
5
DESCRIPTION OF POWER SOURCES AND CLOCK INPUT/OUTPUTS......................................... 19
5.1 3.3 VOLT OPERATION / 5 VOLT TOLERANCE ........................................................................................................19 5.2 POWER FUNCTIONALITY ....................................................................................................................................19 5.2.1 VCC Power .............................................................................................................................................19 5.2.2 VTR Support ...........................................................................................................................................19 5.2.3 Vbat Input ...............................................................................................................................................19 5.3 INTERNAL PWRGOOD.....................................................................................................................................20 5.4 32.768 KHZ TRICKLE CLOCK INPUT...................................................................................................................20 5.5 INDICATION OF 32KHZ CLOCK ...........................................................................................................................20 5.6 XOSEL...........................................................................................................................................................21 5.7 TRICKLE POWER FUNCTIONALITY .......................................................................................................................21 5.8 40MHZ CLOCK OUTPUT....................................................................................................................................23 5.9 MAXIMUM CURRENT VALUES .............................................................................................................................23 5.10 POWER MANAGEMENT EVENTS (PME/SCI) ....................................................................................................23
6
FUNCTIONAL DESCRIPTION............................................................................................................. 24
6.1 SUPER I/O REGISTERS......................................................................................................................................24 6.2 HOST PROCESSOR INTERFACE (LPC) ................................................................................................................24 6.3 LPC INTERFACE ...............................................................................................................................................24 6.3.1 LPC Interface Signal Definition...............................................................................................................25 6.3.2 Power Management................................................................................................................................26 6.3.3 LPC Transfers ........................................................................................................................................27 6.4 FLOPPY DISK CONTROLLER ...............................................................................................................................28 6.4.1 FDC Internal Registers ...........................................................................................................................28 6.4.2 Status Register Encoding .......................................................................................................................38 6.4.3 DMA Transfers........................................................................................................................................41 6.4.4 Controller Phases ...................................................................................................................................41 6.4.5 Command Set/Descriptions ....................................................................................................................42 6.4.6 Instruction Set.........................................................................................................................................45 6.4.7 Data Transfer Commands ......................................................................................................................51 6.4.8 Control Commands.................................................................................................................................57 6.4.9 Direct Support for Two Floppy Drives .....................................................................................................62 6.5 SERIAL PORT (UART) ......................................................................................................................................63 6.5.1 Register Description ...............................................................................................................................63 6.5.2 Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) ................................................70 6.5.3 Effect Of The Reset on Register File ......................................................................................................70 6.5.4 FIFO Interrupt Mode Operation ..............................................................................................................70 6.5.5 FIFO Polled Mode Opertion....................................................................................................................71 6.5.6 Notes On Serial Port Operation ..............................................................................................................75 6.6 INFRARED INTERFACE........................................................................................................................................76 6.6.1 IR Transmit Pin .......................................................................................................................................76 6.7 PARALLEL PORT ...............................................................................................................................................77 6.7.1 IBM XT/AT Compatible, Bi-Directional And EPP Modes........................................................................78 6.7.2 EPP 1.9 Operation..................................................................................................................................80 6.7.3 EPP 1.7 Operation..................................................................................................................................81 6.7.4 Extended Capabilities Parallel Port.........................................................................................................83 6.7.5 Vocabulary..............................................................................................................................................83 6.7.6 ECP Implementation Standard ...............................................................................................................83
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6.7.7 Parallel Port Floppy Disk Controller ........................................................................................................92 6.8 POWER MANAGEMENT ......................................................................................................................................94 6.8.1 FDC Power Management .......................................................................................................................94 6.8.2 UART Power Management.....................................................................................................................96 6.8.3 Parallel Port ............................................................................................................................................96 6.9 REAL TIME CLOCK ............................................................................................................................................97 6.9.1 Configuration Registers ..........................................................................................................................97 6.9.2 Host I/O Interface....................................................................................................................................98 6.9.3 Internal Registers....................................................................................................................................98 6.9.4 Time Calendar and Alarm.......................................................................................................................99 6.9.5 Update Cycle ........................................................................................................................................100 6.9.6 Control and Status Registers ................................................................................................................100 6.9.7 Interrupts ..............................................................................................................................................103 6.9.8 32kHz Clock Input.................................................................................................................................104 6.9.9 Power Management..............................................................................................................................104 6.10 SERIAL IRQ................................................................................................................................................105 6.10.1 Timing Diagrams For SER_IRQ Cycle ..............................................................................................105 6.10.2 Routable IRQ To Serial IRQ Conversion Capability ..........................................................................107 6.11 8042 KEYBOARD CONTROLLER DESCRIPTION................................................................................................108 6.11.1 Keyboard Interface............................................................................................................................108 6.11.2 External Keyboard and Mouse Interface ...........................................................................................109 6.11.3 Keyboard Power Management..........................................................................................................110 6.11.4 Interrupts ...........................................................................................................................................110 6.11.5 Memory Configurations .....................................................................................................................110 6.11.6 Register Definitions ...........................................................................................................................110 6.11.7 External Clock Signal ........................................................................................................................111 6.11.8 Default Reset Conditions ..................................................................................................................111 6.11.9 Latches On Keyboard and Mouse IRQs............................................................................................113 6.11.10 Keyboard and Mouse PME Generation.............................................................................................114 6.12 GENERAL PURPOSE I/O...............................................................................................................................115 6.12.1 GPIO Pins .........................................................................................................................................115 6.12.2 Description ........................................................................................................................................116 6.12.3 GPIO Control.....................................................................................................................................118 6.12.4 GPIO Operation ................................................................................................................................119 6.12.5 GPIO PME and SMI Functionality .....................................................................................................120 6.12.6 Either Edge Triggered Interrupts .......................................................................................................121 6.12.7 LED Functionality ..............................................................................................................................122 6.13 WATCH DOG TIMER.....................................................................................................................................122 6.14 POWER ON ELAPSED TIMER (POET)............................................................................................................123 6.14.1 VCC Power on Elapsed Time Counter..............................................................................................123 6.14.2 VTR Power on Elapsed Time Counter ..............................................................................................123 6.15 FAN SPEED CONTROL AND MONITORING.......................................................................................................124 6.15.1 Fan Speed Control ............................................................................................................................124 6.15.2 Fan Speed Monitoring.......................................................................................................................125 6.16 DEVICE DISABLE REGISTER..........................................................................................................................128 6.16.1 Device Disable Register (LPC only) ..................................................................................................128 6.16.2 SMBus2 Device Disable Register (SMBus2 only) .............................................................................128 6.17 SMBUS CONTROLLER .................................................................................................................................129 6.17.1 Configuration Registers.....................................................................................................................129 6.17.2 Runtime Registers.............................................................................................................................129 6.18 SMBUS2 SLAVE DEVICE..............................................................................................................................135 6.18.1 SMBus Protocols supported by SMBus2 ..........................................................................................136 6.18.2 Command Codes ..............................................................................................................................136 6.18.3 X-Bus SMBus2/LPC Arbitration.........................................................................................................137 6.18.4 SMBus2 Register Summary ..............................................................................................................139 6.18.5 SMBus2 Register Description ...........................................................................................................139 6.18.6 Invalid Command Protocol Response Behavior ................................................................................141 6.18.7 Slave Device Time-Out .....................................................................................................................142 6.18.8 Stretching the SCLK Signal...............................................................................................................142 6.18.9 SMBus Timing...................................................................................................................................142 6.18.10 Bus Reset Sequence ........................................................................................................................142 6.19 X-BUS INTERFACE.......................................................................................................................................143 6.19.1 I/O Cycles .........................................................................................................................................143 6.19.2 Supported LCD Controllers ...............................................................................................................146
SMSC LPC47S45x Page 4 of 259 Rev. 04-30-07
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7
ACPI/PME/SMI FEATURES .............................................................................................................. 147
7.1 POWER STATES..............................................................................................................................................147 7.1.1 Global/System Sleep States .................................................................................................................147 7.1.2 Device Sleep States .............................................................................................................................147 7.1.3 Wake Events ........................................................................................................................................147 7.2 ACPI SPECIFIC REGISTERS .............................................................................................................................148 7.3 ACPI FEATURES ............................................................................................................................................150 7.3.1 Legacy/ACPI Select..............................................................................................................................150 7.3.2 Power Button with Override ..................................................................................................................150 7.3.3 RTC Alarm as a PME Event .................................................................................................................151 7.4 PME SUPPORT ..............................................................................................................................................151 7.4.1 `Wake On Specific Key' Option .............................................................................................................152 7.5 SYSTEM MANAGEMENT INTERRUPT (SMI) .........................................................................................................154 7.5.1 SMI Registers .......................................................................................................................................154 7.5.2 ACPI Support Register for SMI Generation ..........................................................................................155
8
RUNTIME REGISTERS ..................................................................................................................... 156
8.1 8.2 RUNTIME REGISTERS BLOCK SUMMARY............................................................................................................156 RUNTIME REGISTERS BLOCK DESCRIPTION .......................................................................................................160
9
CONFIGURATION ............................................................................................................................. 194
9.1 9.2 9.3 9.4 9.5 SYSTEM ELEMENTS ........................................................................................................................................194 CONFIGURATION SEQUENCE ............................................................................................................................195 PROGRAMMING EXAMPLE ................................................................................................................................195 CHIP LEVEL (GLOBAL) CONTROL/CONFIGURATION REGISTERS[0X00-0X2F].........................................................199 LOGICAL DEVICE CONFIGURATION/CONTROL REGISTERS [0X30-0XFF] ...............................................................202
10
OPERATIONAL DESCRIPTION..................................................................................................... 224
MAXIMUM GUARANTEED RATINGS.................................................................................................................224 DC ELECTRICAL CHARACTERISTICS ..............................................................................................................224
10.1 10.2
11
TIMING DIAGRAMS ....................................................................................................................... 228
11.1 POWER-UP TIMING .....................................................................................................................................229 11.2 INPUT CLOCK TIMING...................................................................................................................................230 11.3 OUTPUT CLOCK TIMING ...............................................................................................................................230 11.4 LPC INTERFACE .........................................................................................................................................231 11.5 FLOPPY DISK TIMING...................................................................................................................................234 11.6 PARALLEL PORT TIMING...............................................................................................................................235 11.6.1 ECP Parallel Port Timing ..................................................................................................................238 11.7 INFRARED INTERFACE TIMING DIAGRAMS.......................................................................................................242 11.8 SMBUS TIMING .........................................................................................................................................246 11.9 X-BUS TIMING ............................................................................................................................................247 11.9.1 Timing For LPC initiated I/O Cycles with the X-Bus ..........................................................................247 11.9.2 Representative LPC I/O Cycle to X-Bus Cycle Timing ......................................................................248 11.9.3 X-Bus Write Cycle: LPC I/O Write Cycle - Data from Host to X-Bus Device .....................................249 11.9.4 Timing For SMBus initiated I/O Cycles with the X-Bus......................................................................250 11.10 TIMING FOR SERIAL IRQ'S ...........................................................................................................................252 11.11 KEYBOARD/MOUSE TIMING ..........................................................................................................................253 11.12 FAN TIMING ................................................................................................................................................254 11.13 TIMING FOR LED OUTPUT............................................................................................................................255
12 13
SMSC 128 PIN QFP PACKAGE OUTLINE, 3.9 MM FOOTPRINT................................................ 256 APPENDIX - TEST MODES ........................................................................................................... 257
13.1 NORMAL OPERATING POWER SUPPLY STATE.................................................................................................257 13.2 TEST MODES..............................................................................................................................................257 13.2.1 Board Test Mode...............................................................................................................................257 13.2.2 XNOR-Chain Test Mode ...................................................................................................................257
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TABLES
Table 1 - Super I/O Block Addresses ..........................................................................................................................24 Table 2 - Status, Data and Control Registers ..............................................................................................................28 Table 3 - Internal 2 Drive Decode - Normal .................................................................................................................32 Table 4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped .....................................................................................32 Table 5 - Tape Select Bits ...........................................................................................................................................32 Table 6 - Drive Type ID ...............................................................................................................................................33 Table 7 - Precompensation Delays .............................................................................................................................34 Table 8 - Data Rates ...................................................................................................................................................34 Table 9 - DRVDEN Mapping0 .....................................................................................................................................34 Table 10 - Default Precompensation Delays ...............................................................................................................35 Table 11 - FIFO Service Delay ....................................................................................................................................36 Table 12 - Status Register 0........................................................................................................................................38 Table 13 - Status Register 1........................................................................................................................................39 Table 14 - Status Register 2........................................................................................................................................40 Table 15 - Status Register 3........................................................................................................................................40 Table 16 - Description of Command Symbols .............................................................................................................42 Table 17 - Instruction Set ............................................................................................................................................45 Table 18 - Sector Sizes ...............................................................................................................................................52 Table 19 - Effects of MT and N Bits.............................................................................................................................52 Table 20 - Skip Bit vs Read Data Command ...............................................................................................................52 Table 21 - Skip Bit vs. Read Deleted Data Command.................................................................................................53 Table 22 - Result Phase Table ....................................................................................................................................54 Table 23 - Verify Command Result Phase Table ........................................................................................................55 Table 24 - Typical Values for Formatting.....................................................................................................................56 Table 25 - Interrupt Identification.................................................................................................................................58 Table 26 - Drive Control Delays (ms) ..........................................................................................................................59 Table 27 - Effects of WGATE and GAP Bits................................................................................................................61 Table 28 - Addressing the Serial Port..........................................................................................................................63 Table 29 - Interrupt Control Table ...............................................................................................................................65 Table 30 - Baud Rates ................................................................................................................................................71 Table 31 - Reset Function Table .................................................................................................................................72 Table 32 - Register Summary for an Individual UART Channel ..................................................................................73 Table 33 - Parallel Port Connector ..............................................................................................................................78 Table 34 - EPP Pin Descriptions .................................................................................................................................82 Table 35 - ECP Pin Descriptions .................................................................................................................................84 Table 36 - ECP Register Definitions............................................................................................................................85 Table 37 - Mode Descriptions......................................................................................................................................85 Table 38A - Extended Control Register .......................................................................................................................88 Table 39 - Channel Commands...................................................................................................................................90 Table 40 - Modified Parallel Port FDD Control ............................................................................................................93 Table 41 - FDC Parallel Port Pins ...............................................................................................................................93 Table 42 - PC/AT and PS/2 Available Registers .........................................................................................................95 Table 43 - State of System Pins in Auto Powerdown ..................................................................................................95 Table 44 - State of Floppy Disk Drive Interface Pins in Powerdown............................................................................96 Table 45 - RTC Configuration Registers .....................................................................................................................97 Table 46 - CMOS Run time Registers .........................................................................................................................98 Table 47 - RTC and CMOS RAM Address Map ..........................................................................................................98 Table 48 - RTC Register Valid Range .........................................................................................................................99 Table 49 - RTC Update Cycle Timing........................................................................................................................100 Table 50 - RTC Divider Selection Bits ......................................................................................................................101 Table 51 - RTC Periodic Interrupt Rates ...................................................................................................................101 Table 52 - I/O Address Map ......................................................................................................................................108 Table 53 - Host Interface Flags .................................................................................................................................109 Table 54 - Status Register.........................................................................................................................................110 Table 55 - Resets ......................................................................................................................................................111 Table 56 - GPIO Pin Functionality .............................................................................................................................115 Table 57 - General Purpose I/O Port Assignments ...................................................................................................117 Table 58 - GPIO Configuration Summary..................................................................................................................119
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DATASHEET
Table 59 - GPIO Read/Write Behavior ......................................................................................................................120 Table 60 - Runtime Register Block Summary - Power On Elapsed Time Counters .................................................123 Table 61 - Different Modes for Fan............................................................................................................................124 Table 62 - SMBus Runtime Registers .......................................................................................................................129 Table 63 - SMBus Control/Status Register (SMBus/Base Address)..........................................................................130 Table 64 - Instruction Table for Serial Bus Control....................................................................................................131 Table 65 - SMBus Own Address Register (SMBus Base Address +1)......................................................................133 Table 66 - SMBus Data Register (SMBus Base Address +2)....................................................................................133 Table 67 - SMBus Clock Register (SMBus Base Address +3) ..................................................................................133 Table 68 - SMBus Clock Select Encoding .................................................................................................................134 Table 69 - Command Codes .....................................................................................................................................137 Table 70 - SMBus2/LPC Arbitration Summary ..........................................................................................................138 Table 71 - SMBus2 Register Mapping Summary ......................................................................................................139 Table 72 - SMBus 2 SMB_COM2 Register Description ............................................................................................139 Table 73 - COM Port 2 Inactive Signal State.............................................................................................................140 Table 74 - SMBus 2 SMB_DDR Register description................................................................................................140 Table 75 - SMBus2, SMB_ARB Arbitration Register .................................................................................................141 Table 76 - LCD Controller Connections.....................................................................................................................146 Table 77 - LCD Controller Operations .......................................................................................................................146 Table 78 - SMI/PME Generation ...............................................................................................................................148 Table 79. Runtime Register Block Summary ............................................................................................................156 Table 80 - Runtime Registers Block Description .......................................................................................................160 Table 81 - LPC47S45x Configuration Registers Summary .......................................................................................196 Table 82 - Chip Level Registers ................................................................................................................................199 Table 83 - Logical Device Registers..........................................................................................................................202 Table 84 - I/O Base Address Configuration Register Description..............................................................................203 Table 85 - Interrupt Select Configuration Register Description..................................................................................206 Table 86 - DMA Channel Select Configuration Register Description.........................................................................206 Table 87 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] ..............................................208 Table 88 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03]..............................................................210 Table 89 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]..............................................................211 Table 90 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]..............................................................211 Table 91 - RTC, Logical Device 6 [Logical Device Number = 0x06] ..........................................................................212 Table 92 - KYBD, Logical Device 7 [Logical Device Number = 0x07] .......................................................................213 Table 93 - X-Bus, Logical Device 8 [Logical Device Number = 0x08] .......................................................................214 Table 94 - Runtime Registers, Logical Device A .......................................................................................................217 Table 95 - SMBus [Logical Device Number = 0x0B] .................................................................................................223
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FIGURES
FIGURE 1 - SERIAL DATA .........................................................................................................................................66 FIGURE 2 - KEYBOARD LATCH ..............................................................................................................................113 FIGURE 3 - MOUSE LATCH.....................................................................................................................................113 FIGURE 4 - GPIO FUNCTION ILLUSTRATION........................................................................................................119 FIGURE 5 - FAN TACHOMETER INPUT AND CLOCK SOURCE............................................................................125 FIGURE 6 - CONCEPTUAL BLOCK DIAGRAM OF FAN MONITORING LOGIC .....................................................126 FIGURE 7 - SAMPLE SMBUS SINGLE BYTE TRANSACTION ...............................................................................135 FIGURE 8 - REPRESENTATIVE DIAGRAM OF SMBUS AND SMBUS2 .................................................................135 FIGURE 9 - WRITE BYTE PROTOCOL....................................................................................................................136 FIGURE 10 - READ BYTE PROTOCOL ...................................................................................................................136 FIGURE 11 - LPC AND SMBUS I/O ACCESSES TO THE X-BUS INTERFACE (MODE 1/MODE 2) ......................145 FIGURE 12 - WAKEUP LOGIC .................................................................................................................................149 FIGURE 13 - POWER-UP TIMING ...........................................................................................................................229 FIGURE 14 - INPUT CLOCK TIMING .......................................................................................................................230 FIGURE 15 - OUTPUT CLOCK TIMING ...................................................................................................................230 FIGURE 16 - PCI CLOCK TIMING............................................................................................................................231 FIGURE 17 - RESET TIMING ...................................................................................................................................231 FIGURE 18 - OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS...................................................231 FIGURE 19 - INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.......................................................232 FIGURE 20 - I/O WRITE ...........................................................................................................................................232 FIGURE 21 - I/O READ.............................................................................................................................................232 FIGURE 22 - DMA REQUEST ASSERTION THROUGH LDRQ#.............................................................................232 FIGURE 23 - DMA WRITE (FIRST BYTE) ................................................................................................................233 FIGURE 24 - DMA READ (FIRST BYTE)..................................................................................................................233 FIGURE 25 - FLOPPY DISK DRIVE TIMING (AT MODE ONLY) .............................................................................234 FIGURE 26 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE ...................................................................................235 FIGURE 27 - EPP 1.9 DATA OR ADDRESS READ CYCLE.....................................................................................236 FIGURE 28 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE ...................................................................................237 FIGURE 29 - EPP 1.7 DATA OR ADDRESS READ CYCLE.....................................................................................237 FIGURE 30 - PARALLEL PORT FIFO TIMING .........................................................................................................239 FIGURE 31 - ECP PARALLEL PORT FORWARD TIMING ......................................................................................240 FIGURE 32 - ECP PARALLEL PORT REVERSE TIMING........................................................................................241 FIGURE 33 - IRDA RECEIVE TIMING.......................................................................................................................242 FIGURE 34 - IRDA TRANSMIT TIMING ...................................................................................................................243 FIGURE 35 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING .............................................................................244 FIGURE 36 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ..........................................................................245 FIGURE 37 - SMBUS TIMING ..................................................................................................................................246 FIGURE 38 - X-BUS READ TIMING .........................................................................................................................247 FIGURE 39 - X-BUS WRITE TIMING........................................................................................................................247 FIGURE 40 - X-BUS AND LPC I/O READ CYCLE....................................................................................................248 FIGURE 41 - X-BUS AND LPC I/O WRITE CYCLE ..................................................................................................249 FIGURE 42 - SMBUS TO X-BUS WRITE CYCLE TIMING FOR LCD AND I/O CYCLES.........................................250 FIGURE 43 - SMBUS TO X-BUS READ CYCLE TIMING FOR LCD AND I/O CYCLES ..........................................251 FIGURE 44 - SETUP AND HOLD TIME....................................................................................................................252 FIGURE 45 - SERIAL PORT DATA ..........................................................................................................................252 FIGURE 46 - KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .......................................................................253 FIGURE 47 - FAN OUTPUT TIMING ........................................................................................................................254 FIGURE 48 - FAN TACHOMTER INPUT TIMING.....................................................................................................254 FIGURE 49 - LED OUTPUT TIMING ........................................................................................................................255 FIGURE 50 - XNOR-CHAIN TEST STRUCTURE.....................................................................................................258
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1
GENERAL DESCRIPTION
The LPC47S45x is a 3.3V PC2001 compliant Super I/O controller designed for server applications. The LPC47S45x implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part provides 55 GPIO pins, ACPI support, an X-Bus interface, two SMBus controllers, a fan speed control output, a fan tachometer input and four ISA IRQs that can be routed to any of the serial IRQs. The LPC47S45x also provides Power on Elapsed Time counters for Main Power and Standby Power, power supply on/off control, and a Real Time Clock. The X-Bus interface allows the LPC47S45x to interface to as many as four external components that have an eight bit data bus and occupy up to 4 contiguous I/O address ports. It is accessible by either the SMBus or the LPC interface. It is capable of interfacing to an LCD Panel Interface Controller without any external logic and it can be used for Port 80h "snooping". The LPC47S45x offers two SMBus controllers that share the same pin interface. The SMBus slave only device provides external access to an LCD controller that can be attached to the X-Bus. It is capable of disabling the floppy port, the serial ports, and the parallel port. The SMBus slave only device can also tristate the Serial Port 2 interface so that it may be muxed with an external UART controller. The LPC47S45x is equipped with two counters that may be monitored either by the SMBus slave only device or by the LPC interface, which monitor the length of time VCC and VTR are active. The LPC47S45x incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, and Intelligent Power Management. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. The on-chip UARTs are compatible with the NS16C550. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47S45x incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The LPC47S45x supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionality to support Windows 2000, Windows Me, and PC2001. The I/O Address, DMA Channel and Hardware IRQ of each logical device in the LPC47S45x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels.
SMSC LPC47S45x
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2
PIN CONFIGURATION
nPS_ON nPB_IN CLKO40 VTR XOSEL XD7/GP17 XD6/GP16 XD5/GP15 XD4/GP14 XD3/GP13 XD2/GP12 XD1/GP11 XD0/GP10 LCDCS XCS1/GP77 nXCS0/GP76 XA3/GP75 XA2/GP74 XA1/GP73 XA0/GP72 nXRD/GP71 nXWR/GP70 VSS SDAT SCLK GP57/nDTR2/SADR1 VTR Vbat XTAL1 XTAL2/CLKI32 AVSS GP40/DRVDEN0 GP41/DRVDEN1 MTR0# DSKCHG# DS0# DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK0# WRTPRT# RDATA# GP42/IO_PME# VCC CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# LPCPD# GP43/DDRC PCI_CLK SER_IRQ VSS GP80 GP81 GP82 GP83 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
LPC47S45x 128 PIN QFP
GP56/nCTS2 GP55/nRTS2/SADR0 GP54/nDSR2 GP53/TXD2/IRTX GP52/RXD2/IRRX GP51/nDCD2 VCC GP50/nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 nDSR1 TXD1 RXD1 nSTROBE nALF nERROR nACK BUSY PE SLCT VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC GP37/A20M GP36/nKBDRST GP35/IRQINB
SMSC LPC47S45x
GP84 GP85 GP86 GP87 GP62/IRQINC GP20/P17/DS1# GP21/P16 GP22/P12/MTR1# GP23/IRQIND GP24/P17 GP25/P12 GP26/SYSOPT GP60/LED1 GP61/LED2 GP27/IO_SMI# GP30/nXCS2 GP31/nXCS3 VTR GP32/FAN_TACH GP33/FAN KDAT KCLK MDAT MCLK VSS GP34/IRQINA
Page 10 of 259
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Rev. 04-30-07
DATASHEET
3
PINOUT
PIN # 1 2 3 4 5 6 7
NAME VTR Vbat XTAL1 XTAL2/CLKI32 AVSS GP40/DRVDEN0 GP41/DRVDEN1
PIN # 33 34 35 36 37 38 39
NAME SER_IRQ VSS GP80 GP81 GP82 GP83 GP84
PIN # 65 66 67 68 69 70 71
NAME GP35/IRQINB GP36/nKBDRST GP37/A20M VCC nINIT nSLCTIN PD0
PIN # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
8 MTR0# 40 GP85 72 PD1 9 DSKCHG# 41 GP86 73 PD2 10 DS0# 42 GP87 74 PD3 11 DIR# 43 GP62/IRQINC 75 PD4 12 STEP# 44 GP20/P17/DS1# 76 PD5 13 WDATA# 45 GP21/P16 77 PD6 14 WGATE# 46 GP22/P12/MTR1# 78 PD7 VSS 15 HDSEL# 47 GP23/IRQIND 79 16 INDEX# 48 GP24/P17 80 SLCT 17 TRK0# 49 GP25/P12 81 PE 18 WRTPRT# 50 GP26/SYSOPT 82 BUSY 19 RDATA# 51 GP60/LED1 83 nACK 20 GP42/IO_PME# 52 GP61/LED2 84 nERROR VCC 21 53 GP27/IO_SMI# 85 nALF 22 CLOCKI 54 GP30/nXCS2 86 nSTROBE 23 LAD0 55 GP31/nXCS3 87 RXD1 VTR 24 LAD1 56 88 TXD1 25 LAD2 57 GP32/FAN_TACH 89 nDSR1 26 LAD3 58 GP33/FAN 90 nRTS1 27 LFRAME# 59 KDAT 91 nCTS1 28 LDRQ# 60 KCLK 92 nDTR1 29 PCI_RESET# 61 MDAT 93 nRI1 30 LPCPD# 62 MCLK 94 nDCD1 VSS 31 GP43/DDRC 63 95 GP50/nRI2 VCC 32 PCI_CLK 64 GP34/IRQINA 96 Note: Pin 4, XTAL2/CLKI32, must not be grounded if XOSEL is floating.
NAME GP51/nDCD2 GP52/RXD2/IRRX GP53/TXD2/IRTX GP54/nDSR2 GP55/nRTS2 /SADR0 GP56/nCTS2 GP57/nDTR2 /SADR1 SCLK SDAT VSS nXWR/GP70 nXRD/GP71 XA0/GP72 XA1/GP73 XA2/GP74 XA3/GP75 nXCS0/GP76 XCS1/GP77 LCDCS XD0/GP10 XD1/GP11 XD2/GP12 XD3/GP13 XD4/GP14 XD5/GP15 XD6/GP16 XD7/GP17 XOSEL VTR CLKO40 nPB_IN nPS_ON
SMSC DS - LPC47S45x
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DATASHEET
4
PIN DESCRIPTION
NAME FUNCTION POWER PINS (12) +3.3 Volt Supply Voltage +3.3 Volt Standby Supply Voltage (Note 6) Ground Analog Ground +3.0 Volt Battery Supply CLOCK PINS (4) 32.768k Hz XTAL1 Terminal 32.768k Hz XTAL2 Terminal/ 32.768kHz Standby Clock Input (Note 3) 14.318MHz Clock Input 40 MHz Clock Output Clock Control Pin (1) Crystal Oscillator Select (Note 12) Power Button Control (2) Power Button Input Power Supply Output FDD INTERFACE (14) General Purpose I/O /Drive Density Select 0 General Purpose I/O /Drive Density Select 1 BUFFER TYPE BUFFER TYPE PER FUNCTION (NOTE 1) POWER WELL
PIN #
21, 68, 96 1, 56, 125 34, 63, 79, 106 5 2 3 4 22 126 124 127 128 6 7
VCC VTR VSS AVSS Vbat XTAL1 XTAL2/CLKI3 2 CLOCKI CLKO40 XOSEL nPB_IN nPS_ON GP40 /DRVDEN0 GP41 /DRVDEN1 nMTR0 nDSKCHG nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ#
IXTL OXTL/I I OP14 I IS OD12 IO12 IO12
IXTL OXTL/I I OP14 I IS OD12 (I/O12/OD12) /(O12/OD12) (I/O12/OD12)/ (O12/OD12)/O1 2 (O12/OD12) IS (O12/OD12) (O12/OD12) (O12/OD12) (O12/OD12) (O12/OD12) (O12/OD12) IS IS IS IS PCI_IO PCI_IO PCI_IO PCI_IO PCI_I PCI_O
Vbat Vbat VCC VTR Vbat VTR (Note 13) VTR VCC VCC (Note 13) VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Rev. 04-30-07
8 9 10 11 12 13 14 15 16 17 18 19 23 24 25 26 27 28
Motor On 0 Disk Change Drive Select 0 Step Direction Step Pulse Write Disk Data Write Gate Head Select Index Pulse Input Track 0 Write Protected Read Disk Data LPC INTERFACE (10) Multiplexed Command Address and Data 0 Multiplexed Command Address and Data 1 Multiplexed Command Address and Data 2 Multiplexed Command Address and Data 3 Frame Encoded DMA Request
Page 12 of 259
O12 IS O12 O12 O12 O12 O12 O12 IS IS IS IS PCI_IO PCI_IO PCI_IO PCI_IO PCI_I PCI_O
SMSC DS - LPC47S45x
DATASHEET
PIN # 29 30 32 33 57 58
NAME PCI_RESET# LPCPD# PCI_CLK SER_IRQ GP32/ FAN_TACH GP33 /FAN
FUNCTION PCI Reset Power Down (Note 2) PCI Clock Serial IRQ FAN CONTROL PINS (2) General Purpose I/O /Fan Tachometer Input General Purpose I/O /Fan Control (Note 4) KEYBOARD/MOUSE (6) Keyboard Data Keyboard Clock Mouse Data Mouse Clock General Purpose I/O /Keyboard Reset (Note 8) General Purpose I/O /Gate A20 (Note 8) PARALLEL PORT INTERFACE (17) Initiate Output/FDC Direction Control Printer Select Input/FDC Step Pulse Port Data 0/FDC Index Port Data 1/FDC Track 0 Port Data 2/FDC Write Protected Port Data 3/FDC Read Disk Data Port Data 4/FDC Disk Change Port Data 5 Port Data 6/FDC Motor On 0 Port Data 7 Printer Selected Status/FDC Write Gate Paper End/FDC Write Data Busy/FDC Motor On Acknowledge/FDC Drive Select 1 Error/FDC Head Select Autofeed Output/FDC Density Select
BUFFER TYPE PCI_I PCI_I PCI_ICL K PCI_IO IO8 IO12
BUFFER TYPE PER FUNCTION (NOTE 1) PCI_I PCI_I PCI_ICLK PCI_IO (I/O8/OD8)/I (I/O12/OD12)/ (O12/OD12) IOD16 IOD16 IOD16 IOD16 (I/O8/OD8) /O8 (I/O8/OD8) /O8
POWER WELL VCC VCC VCC VCC VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC VCC (Note 13) VCC VCC (Note 13) VCC (Note 13) VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
59 60 61 62 66 67
KDAT KCLK MDAT MCLK GP36 /nKBDRST GP37 /A20M
IOD16 IOD16 IOD16 IOD16 IO8 IO8
69 70 71 72 73 74 75 76 77 78 80 81 82 83 84 85
nINIT /nDIR nSLCTIN /nSTEP PD0 /nINDEX PD1 /nTRK0 PD2 /nWRTPRT PD3 /nRDATA PD4 /nDSKCHG PD5 PD6 /nMTR0 PD7 SLCT /nWGATE PE /nWDATA BUSY /nMTR1 nACK /nDS1 nERROR /nHDSEL nALF /nDRVDEN0
OP14 OP14 IS/OP14 IS/OP14 IS/OP14 IS/OP14 IS/OP14 IOP14 IOP14 IOP14 IO12 IO12 IO12 IO12 IO12 OP14
(OD14/OP14) /OD14 (OD14/OP14) /OD14 IOP14/IS IOP14/IS IOP14/IS IOP14/IS IOP14/IS IOP14 IOP14/OD14 IOP14 I/OD12 I/OD12 I/OD12 I/OD12 I/OD12 (OD14/OP14)/ OD14
SMSC DS - LPC47S45x
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DATASHEET
PIN # 86
NAME nSTROBE /nDS0 RXD1 TXD1 nDSR1 nRTS1 nCTS1 nDTR1 nRI1 nDCD1 GP50 /nRI2 GP51 /nDCD2 GP52 /RXD2 /IRRX GP53 /TXD2 /IRTX GP54 /nDSR2 GP55 /nRTS2 /SADR0 GP56 /nCTS2 GP57 /nDTR2 /SADR1 XD0/ GP10 XD1/ GP11 XD2/ GP12 XD3/ GP13 XD4/ GP14 XD5/ GP15 XD6/ GP16 XD7/ GP17
FUNCTION Strobe Output/FDC Drive Select SERIAL PORT 1 INTERFACE (8) Receive Data 1 Transmit Data 1 Data Set Ready 1 Request to Send 1 Clear to Send 1 Data Terminal Ready 1 Ring Indicator 1 Data Carrier Detect 1 SERIAL PORT 2 INTERFACE (8) General Purpose I/O /Ring Indicator 2 General Purpose I/O /Data Carrier Detect 2 General Purpose I/O /Receive Data 2 /IRRX General Purpose I/O /Transmit Data 2 /IRTX (Note 5, 6) General Purpose I/O /Data Set Ready 2 General Purpose I/O /Request to Send 2 /SMBus2 Slave Address 0 General Purpose I/O /Clear to Send 2 General Purpose I/O /Data Terminal Ready 2 /SMBus2 Slave Address 1 X-BUS PINS (18) X-Bus Data Bit 0 /General Purpose I/O X-Bus Data Bit 1 /General Purpose I/O X-Bus Data Bit 2 /General Purpose I/O X-Bus Data Bit 3 /General Purpose I/O X-Bus Data Bit 4 /General Purpose I/O X-Bus Data Bit 5 /General Purpose I/O X-Bus Data Bit 6 /General Purpose I/O X-Bus Data Bit 7 /General Purpose I/O
BUFFER TYPE OP14
BUFFER TYPE PER FUNCTION (NOTE 1) (OD14/OP14)/ OD14 IS O12 I O8 I O6 I I (I/O8/OD8)/I (I/O8/OD8)/I (IS/O8/OD8) /IS (I/O12/OD12) /O12 /O12 (I/O8/OD8) /I (I/O8/OD8) /O8 (I/O8/OD8) /I (I/O8/OD8) /O8
POWER WELL VCC
87 88 89 90 91 92 93 94 95 97 98 99 100 101 102 103
IS O12 I O8 I O6 I I IO8 IO8 IS/O8 IO12 IO8 IO8 IO8 IO8
VCC VCC VCC VCC VCC VCC VCC (Note 13) VCC VCC (Note 13) VCC (Note 13) VCC (Note 13) VTR (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13)
Rev. 04-30-07
116 117 118 119 120 121 122 123
IO8 IO8 IO8 IO8 IO8 IO8 IO8 IO8
IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8)
SMSC DS - LPC47S45x
Page 14 of 259
DATASHEET
PIN # 107 108 109 110 111 112 113 114 54 55
NAME nXWR /GP70 nXRD /GP71 XA0 /GP72 XA1 /GP73 XA2 /GP74 XA3 /GP75 nXCS0/ GP76 XCS1/ GP77 GP30/ nXCS2 GP31/ nXCS3
FUNCTION X-BUS Write (Note 10) /General Purpose I/O X_BUS Read (Note 10) /General Purpose I/O X-BUS Address 0 /General Purpose I/O X-BUS Address 1 /General Purpose I/O X-BUS Address 2 /General Purpose I/O X-BUS Address 3 /General Purpose I/O X-Bus Chip Select 0 /General Purpose I/O X-Bus Chip Select 1(Note 11) /General Purpose I/O General Purpose I/O/ X-Bus Chip Select 2 General Purpose I/O / X-Bus Chip Select 3 LCD PINS (1) LCD Panel Chip Select SMBUS PINS (2) SMBus Clock General Purpose I/O /SMBus Data GENERAL PURPOSE I/O PINS (23) General Purpose I/O / Power Management Event Output General Purpose I/O / Device Disable Reg. Control General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O /IRQ Input C General Purpose I/O / P17 /Drive Select 1
BUFFER TYPE O8 O8 IO8 IO8 IO8 IO8 O8 O8 IO8 IO8
BUFFER TYPE PER FUNCTION (NOTE 1) O8 /(I/O8/OD8) O8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) IO8 /(I/O8/OD8) O8 /(I/O8/OD8) O8 /(I/O8/OD8) (I/O8/OD8)/ O8 (I/O8/OD8)/ O8
POWER WELL VCC VCC VCC VCC VCC VCC VCC VCC VCC (Note 13) VCC (Note 13) VCC VCC VCC VTR VCC (Note 13) VCC VCC VCC VCC VCC VCC VCC VCC VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13)
Rev. 04-30-07
115 104 105 20 31 35 36 37 38 39 40 41 42 43 44
LCDCS SCLK SDAT GP42 /IO_PME# GP43/DDRC GP80 GP81 GP82 GP83 GP84 GP85 GP86 GP87 GP62/IRQINC GP20 /P17/nDS1 GP21 /P16 GP22 /P12 /MTR1# GP23/IRQIND GP24/P17
GP25/P12
O8 IOD12 IOD12 IO12 IO8 IO8 IO8 IO8 IO8 IO8 IO8 IO8 IO8 IO8 IO12
O8 IOD12 IOD12 (I/O12/OD12) /(O12/OD12) (I/O8/OD8)/I (I/O8/OD8) (I/O8/OD8) (I/O8/OD8) (I/O8/OD8) (I/O8/OD8) (I/O8/OD8) (I/O8/OD8) (I/O8/OD8) (I/O8/OD8)/ I (I/O12/OD12)/ IO12/(O12/OD1 2) (I/O8/OD8)/IO8 (I/O12/OD12) /IO12 /(O12/OD12) (I/O8/OD8)/I (I/O8/OD8) /IO8 (I/O8/OD8) /IO8
45 46
General Purpose I/O / P16 General Purpose I/O / P12 /Motor On 1
IO8 IO12
47 48 49
General Purpose I/O /IRQ Input D General Purpose I/O / P17 General Purpose I/O /P12
Page 15 of 259
IO8 IO8 IO8
SMSC DS - LPC47S45x
DATASHEET
PIN # 50 51 52 53 64 65
NAME GP26 /SYSOPT GP60 /LED1 GP61 /LED2 GP27 /IO_SMI# GP34 /IRQINA GP35 /IRQINB
FUNCTION General Purpose I/O /SYSOPT (Note 7) General Purpose I/O /LED1 (Note 9) General Purpose I/O /LED2 (Note 9) General Purpose I/O /IO_SMI# General Purpose I/O / IRQ Input A General Purpose I/O / IRQ Input B
BUFFER TYPE IO8 IO12 IO12 IO12 IO8 IO8
BUFFER TYPE PER FUNCTION (NOTE 1) (I/O8/OD8) (I/O12/OD12)/ (O12/OD12) (I/O12/OD12)/ (O12/OD12) (I/O12/OD12)/ (O12/OD12) (I/O8/OD8)/I (I/O8/OD8)/I
POWER WELL VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13) VCC (Note 13)
Note: The "n" as the first letter of a signal name or the "#" as the suffix of a signal name indicates an "Active Low" signal. Note 1: Buffer types per function on multiplexed pins are separated by a slash "/". Buffer types in parenthesis represent multiple buffer types for a single pin function. Note 2: The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal follows the protocol defined for the LRESET# signal in the "Low Pin Count Interface Specification". Note 3: If the 32kHz input clock is not used and the crystal is not connected, a bit in the configuration register at 0xF0 in Logical Device A, which indicates whether or not the 32KHz clock is connected, should be set to `1'. This bit determines the clock source for the fan tachometer, LED and "wake on specific key" logic. CLKI32 pin MUST not be grounded if XOSEL is left unconnected. Note 4: The fan control pin (FAN) comes up as output and low following a VCC POR and PCI Reset (also known as a Hard Reset). This pin reverts to its non-inverting GPIO input function when VCC is removed from the part. Note 5: The GP53/TXD2/IRTX pin is an output and low when the part is under VTR power (VCC=0). The pin comes up as output and low following a VCC POR and PCI Reset. Note 6: VTR can be connected to VCC if no wakeup functionality is required. Note 7: The GP35/IRQINB/SYSOPT pin requires an external pulldown resistor to put the base I/O address for configuration at 0x02E. An external pullup resistor is required to move the base I/O address for configuration to 0x04E. Note 8: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system must ensure that these pins are high. See Section "Pins That Require External Pullup Resistor". Note 9: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power. The GP61 pin defaults to the LED function active (blinking at a 1 Hz rate, 50% duty cycle) on initial power up (as long as the 32 kHz clock input is active or crystal is connected). Note 10: External pullups are required on the XRD# and XWR# pins. Note 11: XCS1is an active high signal and is designed to be used with supported LCD controllers. Note 12: When XOSEL = `0', the RTC uses a 32.768kHz crystal connected between the XTAL1 and XTAL2 pins. When XOSEL = `1', the RTC is driven by a 32.768kHz single-ended clock source connected to the XTAL2 pin. Note 13: These pins have input buffers into the wakeup logic that are powered by VTR.
SMSC DS - LPC47S45x
Page 16 of 259
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DATASHEET
4.1
Buffer Type Descriptions
Input TTL Compatible. Input with Schmitt Trigger. Output, 6mA sink, 3mA source. Output, 8mA sink, 4mA source. Open Drain Output, 8mA sink. Input/Output, 8mA sink, 4mA source. Input with Schmitt Trigger/Output, 8mA sink, 4mA source. Input/Output, 12mA sink, 6mA source. Input/Output (Open Drain), 12mA sink. Output, 12mA sink, 6mA source. Open Drain Output, 12mA sink. Open Drain Output, 14mA sink. Output, 14mA sink, 14mA source. Input/Output, 14mA sink, 14mA source. Backdrive protected. Input with Schmitt Trigger/Output, 14mA sink, 14mA source. Input/Output (Open Drain), 16mA sink. 32.768 kHz crystal input 32.768 kHz crystal output Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2)
I IS O6 O8 OD8 IO8 IS/O8 IO12 IOD12 O12 OD12 OD14 OP14 IOP14 IS/OP14 IOD16 IXTL OXTL PCI_IO PCI_O PCI_I PCI_ICLK
Note 1: See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. Note 2: See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3.
SMSC DS - LPC47S45x
Page 17 of 259
Rev. 04-30-07
DATASHEET
4.2
Pins That Require External Pullup Resistors
The following pins require external pullup resistors: KDAT KCLK MDAT MCLK GP36/KBDRST if KBDRST function is used GP37/A20M if A20M function is used GP20/P17/DS1# If P17 function is used GP21/P16/P12 if P16 or P12 function is used GP22/P12/MTR1# if P12 function is used GP27/IO_SMI# if IO_SMI# function is used as Open Collector Output GP42/IO_PME# if IO_PME# function is used as Open Collector Output SER_IRQ GP40/DRVDEN0 if DRVDEN0 function is used as Open Collector Output GP41/DRVDEN1/XCS0 if DRVDEN1 function is used as Open Collector Output GP23, GP 34, GP35 and GP62 if IRQINx function is used MTR0# if used as Open Collector Output DS0# if used as Open Collector Output DIR# if used as Open Collector Output STEP# if used as Open Collector Output WDATA# if used as Open Collector Output WGATE# if used as Open Collector Output HDSEL# if used as Open Collector Output INDEX# TRK0# WRTPRT# RDATA# DSKCHG# XRD# XWR# XOSEL if an external single-input 32 kHz clock source is used on the CLKI32 pin (10k pull-up suggested) GP55/nRTS2/SADR0 if SADR0 is used for strapping option (10k pull-up suggested) GP57/nDTR2/SADR1 if SADR1 is used for stapping option (10k pull-up suggested)
SMSC DS - LPC47S45x
Page 18 of 259
Rev. 04-30-07
DATASHEET
5 5.1
DESCRIPTION OF POWER SOURCES AND CLOCK INPUT/OUTPUTS 3.3 Volt Operation / 5 Volt Tolerance
The LPC47S45x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected. The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are: LAD[3:0] LFRAME# LDRQ# LPCPD# The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following LPC Bus pins: PCI_RESET# PCI_CLK SER_IRQ IO_PME#
5.2
5.2.1
Power Functionality
VCC POWER
The LPC47S45x has three power planes: VCC, VTR, and Vbat.
The LPC47S45x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section and the Maximum Current Values subsection.
5.2.2
VTR SUPPORT
The LPC47S45x requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality subsection and the Maximum Current Values subsection. If the LPC47S45x is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a VTR Poweron-Reset signal to initialize these components. Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 s before Vcc begins a power-on cycle. When VTR and Vcc are fully powered, the potential difference between the two supplies must not exceed 500mV.
5.2.3
VBAT INPUT
Vbat is a battery generated power supply that is needed to support the real-time clock and CMOS RAM. The realtime clock keeps updating the time and date in the background even when the system is powered down. The CMOS RAM holds the configurations data, which is read by the ROM BIOS at boot-up. The ROM BIOS reads the real-time clock and the CMOS configuration registers to determine the current configuration as well as time and date. The Vbat supply is 3.0 Volts (nominal). See the Operational Description Section and the Maximum Current Values subsection. The following pins are powered by Vbat: XOSEL XTAL1 XTAL2 The following Runtime Registers are powered by Vbat: VCC Power On Elapsed Time Counter registers at offset 0x6D to 0x70.
SMSC DS - LPC47S45x Page 19 of 259 Rev. 04-30-07
DATASHEET
VTR Power On Elapsed Time Counter registers at offset 0x71 to 0x74. Power Supply Control Register at Logical Device A at offset 0xF8 Power Management 1 Status Register 1 at offset 0x78 Power Management 1 Status Register 2 at offset 0x79 Power Management 1 Enable Register 1 at offset 0x7A Power Management 1 Enable Register 2 at offset 0x7B Power Management 1 Control Register 1 at offset 0x60 Power Management 1 Control Register 2 at offset 0x61 General Purpose Event 1 Enable Register 1 at offset 0x7E General Purpose Event 1 Enable Register 2 at offset 0x7F Note: All Vbat powered pins and registers are powered by VTR when VTR power is on and are battery backed-up when VTR is removed.
5.3
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as Vcc cycles on and off. When the internal PWRGOOD signal is "1" (active), Vcc > 2.3V (nominal), and the LPC47S45x host interface is active. When the internal PWRGOOD signal is "0" (inactive), Vcc 2.3V (nominal), and the LPC47S45x host interface is inactive; that is, LPC bus reads and writes will not be decoded. The LPC47S45x device pins nPB_IN, IO_PME#, XTAL2/CLKI32 and XTAL1, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2, Fan_Tach, and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. The nPS_ON, CLKO40, GP53/TXD2/IRTX, GP60/LED1 and GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality section.
5.4
32.768 KHZ Trickle Clock Input
The LPC47S45x has three different methods of deriving a 32.768kHz signal: From an external crystal oscillator connected accross pins XTAL1 and XTAL2 From an external single-input clock source driven on the CLKI32 pin From an internal PLL that divides down the14MHz clock input to make the 32kHz signal The trickle clock input is used to supply a clock signal for the RTC, 40 MHz clock output, fan tachometer logic, WDT, LED blink and wake on specific key function. See the following section for more information.
5.5
Indication of 32KHZ Clock
There is a bit to indicate whether the 32kHz clock signal is taken from an external 32kHz clock source or derived internally from the 14MHz clock input. This bit is located at Bit[0] of the Clock Select register at 0xF0 in Logical Device A and is referred to as CLK32_PRSN. This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: 0 = Either a single-input 32kHz clock is connected to the CLKI32 pin or a crystal oscillator is connected to the XTAL1and XTAL2 pins (crystal oscillator is default case). Note: The XOSEL pin must be pulled-up if a single-input 32kHz clock source is used. See section 5.6 XOSEL. 1 = Neither the 32kHz clock nor the crystal oscillator are connected. Note: When Bit[0]=1, the 32kHz clock is derived internally from the 14MHz clock input. Note: An external crystal oscillator must be supplied to generate the 32.768kHz clock input for the RTC block under Vbat power.
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Bit[0] controls the source of the 32kHz (nominal) clock for the RTC, 40 MHz clock output, fan tachometer logic, the LED blink logic, the WDT, and the "wake on specific key" logic. When an external 32kHz clock source is connected, that will be the source for the RTC, 40 MHz clock output, fan tachometer, LED, WDT and "wake on specific key" logic. When an external 32kHz clock source is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the RTC, 40MHz clock output, fan tachometer, LED, WDT and "wake on specific key" logic. The following functions will not work under VTR power (VCC removed) if an external 32kHz clock source is not connected. These functions will work under VCC power even if an external 32kHz clock source is not connected. Fan Tachometer Wake on specific key LED blink WDT 40MHz clock output RTC
5.6
XOSEL
The XOSEL signal is used to differentiate between a single-input 32kHz signal driven on the CLKI32 pin or an oscillator connected between XTAL1 and XTAL2. If a single-input 32kHz signal is connected to the CLKI32 pin, the XOSEL pin should be pulled up to VTR. (A 10k pull-up resistor is suggested.) If a crystal oscillator is connected across XTAL1 and XTAL2 then the XOSEL pin should be left unconnected. There is an internal pulldown on this pin that will keep this pin low when not in use. If no external clock source is supplied, then Bit[0] of the Clock Select register found in Logical Device A at offset 0xF0 should be set to `1'. This bit, referred to as CLK32_PRSN, determines if the 32kHz clock source is supplied externally or if it is derived from the 14MHz clock input. The following table summarizes the state of the 32 kHz clock inputs and the XOSEL pin. 32KHZ CLOCK INPUT No external 32kHz clock input or XTAL The 32kHz clock source derived internally from 14MHz input. 32kHz oscillator connected between XTAL1 and XTAL2 (default) (see Note1) Single-input, external 32kHz clock input driven on the CLKI32 pin No external 32kHz clock input or XTAL The 32kHz clock source derived internally from 14MHz input. XOSEL No Connect (see Note1) No Connect (see Note1) Pull-up to VTR Pull-up to VTR BIT[0] (See Note) (CLK32_PRSN) 1 0 0 1
Note: Bit[0] is located in the Clock Select register found in Logical Device A at offset 0xF0. Note 1: When the XOSEL pin is left unconnected (i.e., No Connect), the XTAL2/CLKI32 pin is an output and must not be grounded.
5.7
Trickle Power Functionality
When the LPC47S45x is running under VTR only, the PME wakeup events are active and (if enabled) able to assert the IO_PME# pin active low. The following lists the wakeup events: UART 1 Ring Indicator UART 2 Ring Indicator Keyboard data Mouse data Wake on Specific Key Logic Fan Tachometer (Note) nPB_IN RTC Alarm
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GPIOs for wakeup. See below. Note: The Fan Tachometer can generate a PME when VCC=0. Clear the enable bits for the fan tachometer before removing fan power. The following apply to all I/O pins that are specified to be 5 volt tolerant: I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means at a minimum, they will source their specified current from VTR even when VCC is present. The GPIOs that are used for PME wakeup inputs are GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 - see below): Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR. All GPIOs listed above are for PME wakeup as a GPIO function (or alternate function). Note that GP33 cannot be used for wakeup under VTR power (VCC=0) since this is the fan control pin which comes up as output and low following a VCC POR and PCI Reset. GP53 cannot be used for wakeup under VTR power since this has the IRTX function and comes up as output and low following a VTR POR, a VCC POR and PCI Reset. Also, GP33 reverts to is non-inverting GPIO input function when VCC is removed from the part. GP43 reverts to the basic GPIO function when VCC is removed from the part, but its programmed input/output, invert/non-invert output buffer type is retained. The other GPIOs function as follows: GP40, GP62: Buffers powered by VCC, but in the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered by VTR. These pins are not used for wakeup: GP42, GP53, GP60, GP61: Buffers powered by VTR. GP42 is the IO_PME# pin. GP53 has IRTX as the alternate function and its output buffer is powered by VTR so that the pin is always forced low on VTR POR, VCC POR and PCI Reset. The IRTX pin (GP53/TXD2/IRTX) is powered by VTR so that it are driven low when VCC = 0V with VTR = 3.3V. This pin is driven low on VTR POR, VCC POR and PCI Reset regardless of the selected pin function and regardless of the state of internal PWRGOOD (i.e., when VCC=3.3V and when VCC=0V with VTR=3.3V). The GP53/TXD2/IRTX pin will remain low following a VCC POR until the serial port is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IRCC block. If the TXD2 function is selected for the pin, it will remain low following a VCC POR until the serial port is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the serial port. If the GPIO output function is selected, the pin will reflect the state of the data bit. GP60 and GP61 are used for the LED functions. See the Table in the GPIO section for more information. The following list summarizes the blocks, registers and pins that are powered by VTR: PME interface block Runtime register block (includes all PME, SMI, GPIO and other miscellaneous registers) Configuration Registers "Wake on Specific Key" logic LED control logic Pins for PME Wakeup: GP42/IO_PME# (output, buffer powered by VTR)
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-
nRI1 (input) GP50/nRI2 (input) GP52/RXD2/IRRX (input) KDAT (input) MDAT (input) nPB_IN GPIOs (GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50-GP57, GP60, GP61) - all input-only except GP53, GP60, GP61. See below.
Other Pins GP53/TXD2/IRTX (output, buffer powered by VTR) GP60/LED1 (output, buffer powered by VTR) GP61/LED2 (output, buffer powered by VTR CLKO40 (output, buffer powered by VTR)) nPS_ON (output, buffer powered by VTR)) Note: GP70 to GP77 and GP80 to GP87 are VCC powered I/O pins. They cannot be used for wake-up. Note: The LPC, X-Bus, SMBus, and SMBus2 interface pins are powered by VCC and cannot be used for wake-up.
5.8
40MHz Clock Output
The LPC47S45X offers a 40.5430160 MHz clock output signal at pin 128, referred to as CLKO40. This 40MHz clock source is taken from either the external 32kHz clock source or from the internally derived 32 kHz signal from the 14MHz clock source. The frequency stability of the 40MHz output is 200ppm, max. This 40MHz clock output is powered by VTR and is active (running) following a VTR POR. This clock operates at a 50% duty cycle 20% (i.e. 60/40 or 40/60 duty cycle). This 40MHz clock output can be turned on or off by a bit in a register. This bit is located at Bit[2] of the Clock Select register at 0xF0 in Logical Device A and is referred to as CLKO40_PWR. This register is powered by VTR and reset on a VTR POR. Bit[2] (CLKO40_PWR) is defined as follows: 0 = 40MHz clock output is on (default) 1 = 40MHz clock output is off
5.9
Maximum Current Values
See the "Operational Description" section for the maximum current values. The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or 3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that is driven by VTR. The pins that are powered by VTR include the following: GP42/IO_PME#, GP53/TXD2/IRTX, GP60/LED1, GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving. The maximum VCC current, ICC, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or 3.3V). The maximum Vbat current, IBAT, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or 3.3V).
5.10 Power Management Events (PME/SCI)
The LPC47S45x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME event and SCI event refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 20. PME events are caused by a status bit being set in the PME status registers. These enabled PME events will only generate an IO_PME# signal if the PME_En bit is set in the PME_EN register at offset 02h in the Runtime Register block. SCI events are caused by a status bit being set in the PM1 or GPE status registers. These registers are ACPI
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specific registers, which will generate an IO_PME# signal if the SCI_EN bit is `1' in the PM1_CNTRL1 register at offset 60h. See section 7 ACPI/PME/SMI Features on page 147.
6 6.1
FUNCTIONAL DESCRIPTION Super I/O Registers
The address map, shown below in Table 1, shows the addresses of the different Super I/O blocks immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register.
6.2
Host Processor Interface (LPC)
The host processor communicates with the LPC47S45x through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. Table 1 - Super I/O Block Addresses ADDRESS Base+(0-5) and +(7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) Base+(0-7) Base+(0-7) Base+(0,1) BLOCK NAME Floppy Disk Parallel Port SPP EPP ECP ECP+EPP+SPP Serial Port Com 1 Serial Port Com 2 RTC Bank 0 Bank 1 KYBD X-Bus LOGICAL DEVICE 0 3 NOTES
4 5 6
IR Support
60, 64 7 Base1+0 8 Base2+0 Base3+0 Base4+0 Base + (0-6C) Runtime Registers A Base + (0-3) SMBus B Base + (0-1) Configuration Note 1: Refer to the configuration register descriptions for setting the base address.
6.3
LPC Interface
The LPC interface is used to control all the logical blocks on the LPC47S45x, to communicate with external I/O devices via the X-Bus, and to communicate with SMBus devices via the SMBus master/slave controller. The following sub-sections specify the implementation of the LPC bus. The LPC-to-X-Bus transactions and the LPCto- SMBus transactions are described in sections 6.19 X-Bus Interface and 6.17 SMBus Controller. Since both the LPC interface and the SMBus2 controller can access the X-Bus, an arbitration register has been added to the Runtime Register block at offset 0x77. For a more detailed description of this arbitration, see section 6.18.3 X-Bus SMBus2/LPC Arbitration on page 137.
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6.3.1
LPC INTERFACE SIGNAL DEFINITION
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics. SIGNAL NAME LAD[3:0] LFRAME# PCI_RESET# LDRQ# IO_PME# LPCPD# TYPE I/O Input Input Output OD Input DESCRIPTION
LPC address/data bus. Multiplexed command, address and data bus. Frame signal. Indicates start of new cycle and termination of broken cycle PCI Reset. Used as LPC Interface Reset. Encoded DMA/Bus Master request for the LPC interface. Power Mgt Event signal. Allows the LPC47S45x to request wakeup. Powerdown Signal. Indicates that the LPC47S45x should prepare for power to be shut on the LPC interface. SER_IRQ I/O Serial IRQ. PCI_CLK Input PCI Clock. Note: The CLKRUN# signal is not implemented in this part.
LPC Cycles The following cycle types are supported by the LPC protocol. CYCLE TYPE I/O Write I/O Read DMA Write DMA Read The LPC47S45x ignores cycles that it does not support. Field Definitions The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47S45x. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields. TRANSFER SIZE 1 Byte 1 Byte 1 Byte 1 Byte
LFRAME# Usage LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47S45x to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47S45x monitors the bus to determine whether the cycle is intended for it. The use of LFRAME# allows the LPC47S45x to enter a lower power state internally. There is no need for the LPC47S45x to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks. When the LPC47S45x samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification Revision 1.0.
I/O Read and Write Cycles The LPC47S45x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.
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Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers. See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles. DMA Read and Write Cycles DMA read cycles involve the transfer of data from the host (main memory) to the LPC47S45x. DMA write cycles involve the transfer of data from the LPC47S45x to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47S45x are 1, 2 or 4 bytes. See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles. DMA Protocol DMA on the LPC bus is handled through the use of the LDRQ# lines from the LPC47S45x and special encodings on LAD[3:0] from the host. The DMA mechanism for the LPC bus is described in the following Low Pin Count (LPC) Interface Specification Revision 1.0.
6.3.2
POWER MANAGEMENT
CLOCKRUN Protocol The CLKRUN# pin is not implemented in the LPC47S45x. See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1. LPCPD Protocol See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2. SYNC Protocol See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a table of valid SYNC values. Typical Usage The SYNC pattern is used to add wait states. For read cycles, the LPC47S45x immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47S45x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47S45x will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47S45x uses a SYNC of 0101 for all wait states in a DMA transfer. The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47S45x uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks. SYNC Timeout The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle.
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The LPC47S45x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries. SYNC Patterns and Maximum Number of SYNCS If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8. If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47S45x has protection mechanisms to complete the cycle. This is used for EPP data transfers and utilizes the same timeout protection that is in EPP. SYNC Error Indication The LPC47S45x reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47S45x, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47S45x. If the host was writing data to the LPC47S45x, the data had already been transferred. In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred. I/O and DMA START Fields I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy: When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. When PCI_RESET# goes active (low): the host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal. the LPC47S45x ignores LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high).
6.3.3
LPC TRANSFERS
Wait State Requirements I/O Transfers The LPC47S45x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). DMA Transfers The LPC47S45x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers. See the example timing for the LPC cycles in the "Timing Diagrams" section.
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6.4
Floppy Disk Controller
The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.
6.4.1
FDC INTERNAL REGISTERS
The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. Table 2 - Status, Data and Control Registers PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 Status Register A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDING 0 6 nDRV2 1 5 STEP 0 4 3 2 nTRK0 HDSEL nINDX N/A 0 N/A 1 nWP N/A 0 DIR 0 (Shown with base addresses of 3F0 and 370) SECONDARY ADDRESS R/W REGISTER 370 371 372 373 374 374 375 376 377 377 R R R/W R/W R W R/W R W Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)
RESET COND.
BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.
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BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as "1". BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. PS/2 Model 30 Mode 7 INT PENDING RESET COND. 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 N/A 3 nHDSEL 1 2 INDX N/A 1 WP N/A 0 nDIR 1
BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a PCI or software reset. BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt.
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Status Register B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0
BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a PCI reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a PCI reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a PCI reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1
BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.
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BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. Digital Output Register (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 1 nRESET DRIVE SEL1 0 0 0 DRIVE SEL0 0
RESET COND.
BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported. DRIVE 0 1 DOR VALUE 1CH 2DH
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Table 3 - Internal 2 Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 1 0 1 nDS0 0 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4
Table 4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 1 1 nDS0 1 0 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5
Tape Drive Register (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 5 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 5 - Tape Select Bits TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3
Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are `0'. DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 tape sel1 DB0 tape sel0
REG 3F3
Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive DB1 tape sel1 DB0 tape sel0
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Table 6 - Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 Bit 0 0 0 0 1 1 0 1 1 REGISTER 3F3 - DRIVE TYPE ID Bit 5 Bit 4 L0-CRF2 - B1 L0-CRF2 - B0 L0-CRF2 - B3 L0-CRF2 - B2 L0-CRF2 - B5 L0-CRF2 - B4 L0-CRF2 - B7 L0-CRF2 - B6
Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. Data Rate Select Register (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A PCI reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0
RESET COND.
BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a PCI reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime register block.
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Table 7 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 PRECOMPENSATION DELAY (nsec) <2Mbps 2Mbps 0 0.00 20.8 41.67 41.7 83.34 62.5 125.00 83.3 166.67 104.2 208.33 125 250.00 Default Default Default: See Table 10
Table 8 - Data Rates DRIVE RATE DRT1 DRT0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SEL1 SEL0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 DATA RATE MFM FM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 --250 150 125 --250 250 125 --250 --125 DENSEL 1 1 0 0 1 1 0 0 1 1 0 0 DRATE(1) 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0
Drive Rate Table (Recommended)
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins. Table 9 - DRVDEN Mapping0 DT1 0 DT0 0 DRVDEN1 (1) DRATE0 DRVDEN0 (1) DENSEL DRIVE TYPE 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2
1 0 1
0 1 1
DRATE0 DRATE0 DRATE1
DRATE1 nDENSEL DRATE0
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Table 10 - Default Precompensation Delays DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps Main Status Register Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer. 7 RQM 6 DIO 5 NON DMA 4 CMD BUSY 3 2 1 DRV1 BUSY 0 DRV0 BUSY PRECOMPENSATIO N DELAYS 20.8 ns 41.67 ns 125 ns 125 ns 125 ns
Reserved Reserved
BIT 0 - 1 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte. BIT 5 NON-DMA Reserved, read `0'. This part does not support non-DMA mode. BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0. Data Register (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 11 gives several examples of the delays with a FIFO. The data is based upon the following formula: Threshold # x 1 DATA RATE x 8 - 1.5 s = DELAY
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At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. Table 11 - FIFO Service Delay FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES
1 byte 2 bytes 8 bytes 15 bytes
MAXIMUM DELAY TO SERVICING AT 2 Mbps DATA RATE 1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s MAXIMUM DELAY TO SERVICING AT 1 Mbps DATA RATE
1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s
FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes Digital Input Register (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG N/A 6 0 N/A 5 0 N/A
MAXIMUM DELAY TO SERVICING AT 500 Kbps DATA RATE 1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s
4 0 N/A
3 0 N/A
2 0 N/A
1 0 N/A
0 0 N/A
RESET COND.
BIT 0 - 6 UNDEFINED The data bus outputs D0 - 6 are read as `0'. BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
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PS/2 Mode 7 DSK CHG N/A 6 1 N/A 5 1 N/A 4 1 N/A 3 1 N/A 2 1 0 DRATE DRATE nHIGH SEL1 SEL0 nDENS N/A N/A 1
RESET COND.
BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a PCI reset. BITS 3 - 6 UNDEFINED Always read as a logic "1" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E). Model 30 Mode 7 DSK CHG N/A 6 0 0 5 0 0 4 0 0 3 2 1 0 DMAEN NOPREC DRATE DRATE SEL1 SEL0 0 0 1 0
RESET COND.
BITS 0 - 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a PCI reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BITS 4 - 6 UNDEFINED Always read as a logic "0" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
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Configuration Control Register (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 0 N/A 1 0 DRATE DRATE SEL1 SEL0 1 0
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values. BIT 2 - 7 RESERVED Should be set to a logical "0". PS/2 Model 30 Mode 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 1 0 NOPREC DRATE DRATE SEL1 SEL0 N/A 1 0
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT 3 - 7 RESERVED Should be set to a logical "0" Table 9 shows the state of the DENSEL pin. The DENSEL pin is set high after a PCI reset and is unaffected by the DOR and the DSR resets.
6.4.2
STATUS REGISTER ENCODING
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 12 - Status Register 0 BIT NO. 7,6 SYMBOL IC NAME DESCRIPTION Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. Seek End The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command).
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5
SE
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DATASHEET
BIT NO. 4
SYMBOL EC
3 2 1,0
H DS1,0
DESCRIPTION The TRK0 pin failed to become a "1" after: 1. 80 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". Head Address The current head address. Drive Select The current selected drive. Table 13 - Status Register 1
NAME Equipment Check
BIT NO. 7
SYMBOL EN
NAME End of Cylinder
6 5 4
DE OR
Data Error Overrun/ Underrun
3 2
ND
No Data
1 0
NW MA
Not Writeable Missing Address Mark
DESCRIPTION The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0". Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. Any one of the following: 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the nINDEX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track.
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Table 14 - Status Register 2 BIT NO. 7 6 SYMBOL CM NAME Control Mark DESCRIPTION Unused. This bit is always "0". Any one of the following: Read Data command - the FDC encountered a deleted data address mark. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field. The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. The FDC cannot detect a data address mark or a deleted data address mark.
5 4 3 2 1
DD WC
Data Error in Data Field Wrong Cylinder
BC
Bad Cylinder
0
MD
Missing Data Address Mark
Table 15 - Status Register 3 BIT NO. 7 6 5 4 3 2 1,0 HD DS1,0 Drive Select T0 Track 0 WP Write Protected SYMBOL NAME DESCRIPTION Unused. This bit is always "0". Indicates the status of the WP pin. Unused. This bit is always "1". Indicates the status of the TRK0 pin. Unused. This bit is always "1". Head Address Indicates the status of the HDSEL pin. Indicates the status of the DS1, DS0 pins.
RESET There are three sources of system reset on the FDC: the PCI_RESET# pin, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a PCI_RESET#, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. PCI_RESET# Pin (Hardware Reset) The PCI_RESET# pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state.
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MODES OF OPERATION The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the Interface Mode bits in LD0-CRF0[3,2]. PC/AT mode The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal. PS/2 mode This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care". The DMA and interrupt functions are always enabled, and DENSEL is an active low. Model 30 mode This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.
6.4.3
DMA TRANSFERS
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: single Transfer and Burst Transfer. Burst mode is enabled via Logical Device 0-CRF0-Bit[1] (LD0-CRF0[1]).
6.4.4
CONTROLLER PHASES
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. Command Phase After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 16 for the command set descriptions). These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition. Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by an read/write or DMA cycle depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. Non-DMA Mode - Transfers from the FIFO to the Host This part does not support non-DMA mode.
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Non-DMA Mode - Transfers from the Host to the FIFO This part does not support non-DMA mode. DMA Mode - Transfers from the FIFO to the Host The FDC generates a DMA request cycle when the FIFO contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by generating the proper sync for the data transfer. DMA Mode - Transfers from the Host to the FIFO. The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA controller must respond by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more data is required. Data Transfer Termination The FDC supports terminal count explicitly through the TC cycle and implicitly through the underrun/overrun and end-oftrack (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions and TC cycle is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. Note: when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. Result Phase The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command.
6.4.5
COMMAND SET/DESCRIPTIONS
Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 16 for explanations of the various symbols used. Table 17 lists the required parameters and the results associated with each command that the FDC is capable of performing. Table 16 - Description of Command Symbols SYMBOL C D D0, D1 NAME Cylinder Address Data Pattern Drive Select 0-1 DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle.
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DIR
Direction Control
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Table 16 - Description of Command Symbols SYMBOL DS0, DS1 NAME Disk Drive Select DESCRIPTION DS1 DS0 DRIVE 0 0 Drive 0 0 1 Drive 1 By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. The final sector number of the current track. Alters Gap 2 length when using Perpendicular Mode. The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0.
DTL
Special Sector Size
EC EFIFO EIS
Enable Count Enable FIFO Enable Implied Seek End of Track Gap Length Head Address Head Load Time
EOT GAP GPL H/HDS HLT
HUT
Head Unload Time
LOCK
MFM MT
MFM/FM Mode Selector Multi-Track Selector
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Table 16 - Description of Command Symbols SYMBOL N NAME Sector Size Code DESCRIPTION This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N SECTOR SIZE 00 128 Bytes 01 256 Bytes 02 512 Bytes 03 1024 Bytes ... ... 07 16K Bytes The desired cylinder number. Write `0'. This part does not support non-DMA mode. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH.
NCN ND OW PCN POLL PRETRK
New Cylinder Number Non-DMA Mode Flag Overwrite Present Cylinder Number Polling Disable Precompensation Start Track Number Sector Address
R
RCN SC
Relative Cylinder Number Number of Sectors Per Track Skip Flag
SK
SRT
Step Rate Interval
ST0 ST1 ST2 ST3 WGATE
Status 0 Status 1 Status 2 Status 3 Write Gate
The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative cylinder offset from present cylinder as used by the Relative Seek command. The number of sectors per track to be initialized by the Format command. The number of sectors per track to be verified during a Verify command when EC is set. When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays. Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. Alters timing of WE to allow for pre-erase loads in perpendicular drives.
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6.4.6
INSTRUCTION SET
Table 17 - Instruction Set READ DATA DATA BUS REMARKS D6 D5 D4 D3 D2 D1 D0 MFM SK 0 0 1 1 0 Command Codes 0 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N
PHASE Command
R/W W W W W W W W W W D7 MT 0
Execution Result R R R R R R R
PHASE Command
R/W W W W W W W W W W D7 MT 0
Execution Result R R R R R R R
SMSC DS - LPC47S45x
READ DELETED DATA DATA BUS REMARKS D6 D5 D4 D3 D2 D1 D0 MFM SK 0 1 1 0 0 Command Codes 0 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N
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PHASE Command
R/W W W W W W W W W W D7 MT 0
Execution Result R R R R R R R
WRITE DATA DATA BUS REMARKS D6 D5 D4 D3 D2 D1 D0 MFM 0 0 0 1 0 1 Command Codes 0 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N
PHASE Command
R/W W W W D7 MT 0
WRITE DELETED DATA DATA BUS D6 D5 D4 D3 D2 D1 MFM 0 0 1 0 0 0 0 0 0 HDS DS1 C
REMARKS D0 1 DS0 Command Codes Sector ID information prior to Command execution.
W W W W W W Execution Result R R R R
H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Command execution.
ST0 ST1 ST2 C
Sector ID information after Command execution.
R R R
H R N
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PHASE Command
R/W W W W D7 0 0
READ A TRACK DATA BUS D6 D5 D4 D3 D2 D1 MFM 0 0 0 0 1 0 0 0 0 HDS DS1 C
REMARKS D0 0 DS0 Command Codes Sector ID information prior to Command execution.
W W W W W W Execution
H R N EOT GPL DTL Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Status information after Command execution.
Result
R R R R
ST0 ST1 ST2 C
Sector ID information after Command execution.
R R R
H R N
PHASE Command
R/W W W W W W W W W W D7 MT EC
VERIFY DATA BUS D6 D5 D4 D3 D2 D1 MFM SK 1 0 1 1 0 0 0 0 HDS DS1 C H R N EOT GPL DTL/SC ST0 ST1 ST2 C H R N
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REMARKS D0 0 DS0 Command Codes Sector ID information prior to Command execution.
Execution Result R R R R R R R
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No data transfer takes place. Status information after Command execution. Sector ID information after Command execution.
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PHASE Command Result
R/W W R D7 0 1 D6 0 0 D5 0 0
VERSION DATA BUS D4 D3 D2 1 0 0 1 0 0
REMARKS D1 0 0 D0 0 0 Command Code Enhanced Controller
PHASE Command
R/W W W W W W W W D7 0 0
FORMAT A TRACK DATA BUS REMARKS D6 D5 D4 D3 D2 D1 D0 MFM 0 0 1 1 0 1 Command Codes 0 0 0 0 HDS DS1 DS0 N Bytes/Sector SC Sectors/Cylinder GPL Gap 3 D Filler Byte C Input Sector Parameters
Execution for Each Sector Repeat:
W W W
H R N FDC formats an entire cylinder Status information after Command execution
Result
R R R R R R R
ST0 ST1 ST2 Undefined Undefined Undefined Undefined
PHASE Command Execution
R/W W W D7 0 0 D6 0 0
RECALIBRATE DATA BUS D5 D4 D3 D2 0 0 0 1 0 0 0 0
REMARKS D1 D0 1 1 Command Codes DS1 DS0 Head retracted to Track 0 Interrupt.
PHASE Command Result
R/W W R D7 0
SENSE INTERRUPT STATUS DATA BUS D6 D5 D4 D3 D2 D1 0 0 0 1 0 0 ST0
REMARKS D0 0 Command Codes Status information at the end of each seek operation.
R
PCN
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PHASE Command
R/W W W W D7 0
SPECIFY DATA BUS D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 1 SRT HUT HLT ND
REMARKS Command Codes
PHASE Command Result
R/W W W R D7 0 0 D6 0 0
SENSE DRIVE STATUS DATA BUS D5 D4 D3 D2 D1 0 0 0 1 0 0 0 0 HDS DS1 ST3
REMARKS D0 0 DS0 Command Codes Status information about FDD
PHASE Command
R/W W W W D7 0 0
SEEK DATA BUS D6 D5 D4 D3 D2 D1 0 0 0 1 1 1 0 0 0 0 HDS DS1 NCN
REMARKS D0 1 DS0 Command Codes
Execution
Head positioned over proper cylinder on diskette.
PHASE Command
R/W W W W D7 0 0 0 D6 0 0 EIS
CONFIGURE DATA BUS D5 D4 D3 0 1 0
REMARKS D2 0 D1 1 D0 1 Configure Information
Execution
W
0 0 0 0 0 0 FIFOTHR EFIF POL O L PRETRK
RELATIVE SEEK DATA BUS PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 D4 D3 D2 D1 0 0 1 1 1 0 0 0 HDS DS1 RCN D0 1 DS0 REMARKS
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PHASE Command Execution Result
R/W W D7 0 D6 0
DUMPREG DATA BUS D5 D4 D3 0 0 1
REMARKS D2 1 D1 1 D0 0 *Note: Registers placed in FIFO
R R R R R R R R R R
PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3 SRT HUT HLT ND SC/EOT LOCK 0 D3 D2 D1 D0 GAP WGATE 0 EIS EFIF POLL FIFOTHR O PRETRK
PHASE Command Execution
R/W W W D7 0 0 D6 MFM 0
READ ID DATA BUS D5 D4 D3 0 0 1 0 0 0
REMARKS D2 0 HDS D1 1 DS1 D0 0 DS0 Commands The first correct ID information on the Cylinder is stored in Data Register Status information after Command execution.
Result
R
ST0
Disk status after the Command has completed R R R R R R ST1 ST2 C H R N
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PHASE Command
R/W W D7 0 OW D6 0 0
PERPENDICULAR MODE DATA BUS D5 D4 D3 D2 D1 0 1 0 0 1 D3 D2 D1 D0 GA P
REMARKS D0 0 WGATE Command Codes
PHASE Command
R/W D7 W
INVALID CODES DATA BUS D6 D5 D4 D3 D2 D1 Invalid Codes
REMARKS D0 Invalid Command Codes (NoOp FDC37C669FRLV goes into Standby State) ST0 = 80H
Result
R
ST0
PHASE Command Result
R/W W R D7 LOCK 0 D6 0 0 D5 0 0
LOCK DATA BUS D4 D3 1 0 LOCK 0
REMARKS D2 1 0 D1 0 0 D0 0 0 Command Codes
SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
6.4.7
DATA TRANSFER COMMANDS
All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed. Read Data A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 18 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For
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writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. Table 18 - Sector Sizes N 00 01 02 03 .. 07 SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes
The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 19. At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 21 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 20, the C or R value of the sector address is automatically incremented (see Table 22). Table 19 - Effects of MT and N Bits MT 0 1 0 1 0 1 N 1 1 2 2 3 3 MAXIMUM TRANSFER CAPACITY 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 FINAL SECTOR READ FROM DISK 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1
Table 20 - Skip Bit vs Read Data Command SK BIT VALUE DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ? Yes Yes CM BIT OF ST2 SET? No Yes RESULTS DESCRIPTION OF RESULTS Normal termination. Address not incremented. Next sector not searched for.
0 0
Normal Data Deleted Data
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SK BIT VALUE
DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ? Yes No CM BIT OF ST2 SET? No Yes
RESULTS DESCRIPTION OF RESULTS Normal termination. Normal termination. Sector not read ("skipped").
1 1
Normal Data Deleted Data
Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 21 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 21, the C or R value of the sector address is automatically incremented (see Table 22). Table 21 - Skip Bit vs. Read Deleted Data Command SK BIT VALUE DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ? 0 Normal Data Yes CM BIT OF ST2 SET? Yes
RESULTS DESCRIPTION OF RESULTS Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). Normal termination.
0 1
Deleted Data Normal Data
Yes No
No Yes
1
Deleted Data
Yes
No
Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a "1" if there no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0". This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command.
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Table 22 - Result Phase Table MT 0 HEAD 0 1 1 0 1 FINAL SECTOR TRANSFERRED TO HOST Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT ID INFORMATION AT RESULT PHASE C H R N NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC NC LSB 01 NC NC NC R+1 NC C+1 LSB 01 NC
NC: No Change, the same value as the one at the beginning of command execution.
LSB: Least Significant Bit, the LSB of H is complemented. Write Data After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command
Definition of DTL when N = 0 and when N does not = 0 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk. Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 22 and Table 23 for information concerning the values of MT and EC versus SC and EOT value.
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Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1". Table 23 - Verify Command Result Phase Table MT 0 0 0 0 1 1 1 1 EC 0 0 1 1 0 0 1 1 SC/EOT VALUE SC = DTL EOT <= # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC <= # Sectors Remaining AND EOT <= # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT <= # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC <= # Sectors Remaining AND EOT <= # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side TERMINATION RESULT Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid
Note: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command. Table 24 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics.
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FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S N C GAP2 SYNC EOR 22x 12x C C 4E 00 DATA AM C DATA R GAP3 GAP 4b C
3x FC C2
3x FE A1
3x FB A1 F8
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4a 40x FF SYNC 6x 00 IAM GAP1 SYNC 26x 6x FF 00 IDAM C Y L H D S N C GAP2 SYNC 11x 6x EOR C C FF 00 DATA AM C DATA R GAP3 GAP 4b C
FC
FE
FB or F8
PERPENDICULAR FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S N C GAP2 SYNC EOR 41x 12x C C 4E 00 DATA AM C DATA R GAP3 GAP 4b C
3x FC C2
3x FE A1
3x FB A1 F8
Table 24 - Typical Values for Formatting SECTOR SIZE N SC GPL1 GPL2 09 07 12 00 128 19 10 10 00 128 30 18 08 02 512 87 46 04 03 1024 FM FF C8 02 04 2048 FF C8 01 05 4096 5.25" Drives ... ... 0C 0A 12 01 256 32 20 10 01 256 50 2A 09 02 512* F0 80 04 03 1024 MFM FF C8 02 04 2048 FF C8 01 05 4096 ... ... 128 0 0F 07 1B 3.5" FM 256 1 09 0F 2A Drives 512 2 05 1B 3A 36 0E 0F 1 256 54 1B 09 2 MFM 512** 74 35 05 3 1024 GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note: All values except sector size are in hex. FORMAT
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6.4.8
CONTROL COMMANDS
Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as the nTRK0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTRK0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 80 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller. Seek The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: Direction signal to drive set to "1" (step in) and issues step pulses. PCN > NCN: Direction signal to drive set to "0" (step out) and issues step pulses. The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) 2) 3) 4) Seek command - Step to the proper track Sense Interrupt Status command - Terminate the Seek command Read ID - Verify head is on proper track Issue Read/Write command.
The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command.
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Sense Interrupt Status An interrupt signal is generated by the FDC for one of the following reasons: 1. Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command h. Verify command 2. End of Seek, Relative Seek, or Recalibrate command The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. Table 25 - Interrupt Identification SE 0 1 IC 11 00 INTERRUPT DUE TO Polling Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate command
1
01
The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 26. The values are the same for MFM and FM. A DMA operation is selected by the ND bit. When ND is "0", the DMA mode is selected. This part does not support non-DMA mode. In DMA mode, data transfers are signaled by the DMA request cycles.
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Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. Table 26 - Drive Control Delays (ms) HUT 500K 300K 426 256 26.7 16 .. .. 373 224 400 240 SRT 500K 300K 26.7 16 25 15 .. .. 3.33 2 1.67 1
0 1 .. E F
2M 64 4 .. 56 60
1M 128 8 .. 112 120
250K 512 32 .. 448 480
2M 4 3.75 .. 0.5 0.25 HLT
1M 8 7.5 .. 1 0.5
250K 32 30 .. 4 2
00 01 02 .. 7F 7F
2M 64 0.5 1 .. 63 63.5
1M 128 1 2 .. 126 127
500K 256 2 4 .. 252 254
300K 426 3.3 6.7 .. 420 423
250K 512 4 8 . 504 508
Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes. PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte.
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Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR - Head Step Direction Control RCN - Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. DIR 0 1 ACTION Step Head Out Step Head In
The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command. Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 27 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The Format Fields table illustrates the change in the Gap2 field size for the perpendicular format.
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On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write precompensation values. When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. The write pre-compensation given to a perpendicular mode drive will be 0ns. 3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. Note: Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1" then D0D3 are ignored. Software and hardware (PCI) resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. 2. PCI resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e all conventional mode. Table 27 - Effects of WGATE and GAP Bits PORTION OF GAP 2 WRITTEN BY WRITE DATA OPERATION 0 Bytes 19 Bytes 0 Bytes 38 Bytes
WGATE 0 0 1 1
MODE GAP Conventional 0 Perpendicular 1 (500 Kbps) Reserved 0 (Conventional) Perpendicular 1 (1 Mbps)
LENGTH OF GAP2 FORMAT FIELD 22 Bytes 22 Bytes 22 Bytes 41 Bytes
LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software
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should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the PCI_RESET# pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte. Enhanced DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. Compatibility The LPC47S45x was designed with software compatibility in mind. It is a fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a PCI reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.
6.4.9
DIRECT SUPPORT FOR TWO FLOPPY DRIVES
The MTR1# function is on pin 43. MTR1# is the second alternate function on the GP22 pin. Pin 43 has IO12 buffer type. The MTR1# function is selectable as open drain or push pull as MTR0# is through bit 6 of the FDD Mode Register in CRF0 of LD 0. This overrides the selection of the output type through bit 7 of the GPIO control register. It is also controlled by bit 7 of the FDD Mode Register. The DS1# function is on pin 41. DS1# is the second alternate function on the GP20 pin. Pin 41 has IO12 buffer type. The DS1# function is selectable as open drain or push pull as DS0# is through bit 6 of the FDD Mode Register in CRF0 of LD 0. This overrides the selection of the output type through bit 7 of the GPIO control register. It is also controlled by bit 7 of the FDD Mode register. See the Runtime Registers section for register information. Disk Change Support for Second Floppy Bit[1] in the Force Disk Change register supports the second floppy. Setting either of the Force Disk Change bits active forces the internal FDD nDSKCHG active when the appropriate drive has been selected. The Force Disk Change register is defined in the Runtime Registers section. Force Write Protect Support for Second Floppy Bit[0] in the Device Disable register and FDD Option register support floppy write protect. See the Runtime Registers section for Device Disable register description and the Configuration Registers section for FDD Option register description.
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6.5
Serial Port (UART)
The LPC47S45x incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-toserial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA 1.0, HP-SIR, ASK-IR infrared modes of operation. Note: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more information.
6.5.1
REGISTER DESCRIPTION
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The LPC47S45x contains two serial ports, each of which contain a register set as described below. Table 28 - Addressing the Serial Port DLAB* A2 A1 A0 REGISTER NAME 0 0 0 0 Receive Buffer (read) 0 0 0 0 Transmit Buffer (write) 0 0 0 1 Interrupt Enable (read/write) X 0 1 0 Interrupt Identification (read) X 0 1 0 FIFO Control (write) X 0 1 1 Line Control (read/write) X 1 0 0 Modem Control (read/write) X 1 0 1 Line Status (read/write) X 1 1 0 Modem Status (read/write) X 1 1 1 Scratchpad (read/write) 1 0 0 0 Divisor LSB (read/write) 1 0 0 1 Divisor MSB (read/write *Note: DLAB is Bit 7 of the Line Control Register The following section describes the operation of the registers. Receive Buffer Register (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible. Transmit Buffer Register (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. Interrupt Enable Register (IER)
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Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47S45x. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". Bit 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state. Bits 4 through 7 These bits are always logic "0". FIFO Control Register (FCR) Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x1D). Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. Bit 4,5 Reserved
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Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt. RCVR FIFO Trigger Level (BYTES) 1 4 8 14
Bit 7 0 0 1 1 Interrupt Identification Register (IIR) Address Offset = 2H, DLAB = X, READ
Bit 6 0 1 0 1
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 1. 2. 3. 4. Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table. Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic "0". Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. Table 29 - Interrupt Control Table FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 0 1 BIT 1 0 1
INTERRUPT SET AND RESET FUNCTIONS PRIORITY INTERRUPT INTERRUPT INTERRUPT LEVEL TYPE SOURCE RESET BIT 0 CONTROL 1 None None 0 Highest Receiver Line Overrun Error, Reading the Line Status Parity Error, Status Register Framing Error or Break Interrupt
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FIFO MODE ONLY BIT 3 0
INTERRUPT IDENTIFICATION REGISTER BIT 2 1 BIT 1 0 PRIORITY LEVEL BIT 0 0 Second
1
1
0
0
Second
0
0
1
0
Third
0
0
0
0
Fourth
INTERRUPT SET AND RESET FUNCTIONS INTERRUPT INTERRUPT INTERRUPT TYPE SOURCE RESET CONTROL Received Data Receiver Data Read Receiver Available Available Buffer or the FIFO drops below the trigger level. Character No Characters Reading the Timeout Have Been Receiver Buffer Indication Removed From or Register Input to the RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time Transmitter Transmitter Reading the IIR Holding Holding Register Register (if Source Register Empty Empty of Interrupt) or Writing the Transmitter Holding Register MODEM Clear to Send or Reading the Status Data Set Ready or MODEM Status Ring Indicator or Register Data Carrier Detect
Line Control Register (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE
Start
LSB Data 5-8 bits MSB
Parity
Stop
FIGURE 1 - SERIAL DATA This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: The Start, Stop and Parity bits are not included in the word length. BIT 1 0 0 1 1 BIT 0 0 1 0 1 WORD LENGTH 5 Bits 6 Bits 7 Bits 8 Bits
Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information.
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BIT 2 0 1 1 1 1
WORD LENGTH -5 bits 6 bits 7 bits 8 bits
NUMBER OF STOP BITS 1 1.5 2 2 2
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3 Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). Bit 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. Bit 5 Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as 0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled. Bit 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. Modem Control Register (MCR) Address Offset = 4H, DLAB = X, READ/WRITE This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1". Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled.
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Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: The TXD is set to the Marking State (logic "1"). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD). The Modem Control output pins are forced inactive high. Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7 These bits are permanently set to logic zero. Line Status Register (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrunn error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled.
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Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty. Bit 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO. Modem Status Register (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. Note: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated. Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR. Scratchpad Register (SCR)
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Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily.
6.5.2
PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL)
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 30 shows the baud rates.
6.5.3
EFFECT OF THE RESET ON REGISTER FILE
The Reset Function Table (Table 31) details the effect of the Reset input on each of the registers of the Serial Port.
6.5.4
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: A. A FIFO timeout interrupt occurs if all the following conditions exist: At least one character is in the FIFO. The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay). The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baudrate). C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
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Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
6.5.5
FIFO POLLED MODE OPERTION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled. Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. Table 30 - Baud Rates DESIRED DIVISOR USED TO PERCENT ERROR DIFFERENCE GENERATE 16X CLOCK BETWEEN DESIRED AND ACTUAL1 BAUD RATE 50 2304 0.001 75 1536 110 1047 134.5 857 0.004 150 768 300 384 600 192 1200 96 1800 64 2000 58 0.005 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 0.030 57600 2 0.16 115200 1 0.16 230400 32770 0.16 460800 32769 0.16 Note1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%. Note 2: The High Speed bit is located in the Device Configuration Space. HIGH SPEED BIT2 X X X X X X X X X X X X X X X X X X X 1 1
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Table 31 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET RESET RESET/ FCR1*FCR0/_FCR0 RESET/ FCR1*FCR0/_FCR0 RESET STATE All bits low Bit 0 is high; Bits 1 - 7 low All bits low All bits low All bits low All bits low except 5, 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low High High High High All Bits Low
All Bits Low
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Table 32 - Register Summary for an Individual UART Channel REGISTER ADDRESS* ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0 REGISTER NAME Receive Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register REGISTER SYMBOL RBR THR IER BIT 0 Data Bit 0 (Note 1) Data Bit 0 Enable Received Data Available Interrupt (ERDAI) BIT 1 Data Bit 1 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt ID Bit
ADDR = 2
Interrupt Ident. Register (Read Only)
IIR
ADDR = 2 ADDR = 3
FIFO Control Register (Write Only) Line Control Register
FCR (Note 7) LCR
"0" if Interrupt Pending FIFO Enable RCVR FIFO Reset Word Word Length Length Select Bit 0 Select Bit 1 (WLS0) (WLS1) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send (DCTS) Bit 0 Bit 0 Bit 8 Request to Send (RTS)
ADDR = 4
MODEM Control Register
MCR
ADDR = 5 ADDR = 6
Line Status Register MODEM Status Register
LSR MSR
Overrun Error (OE) Delta Data Set Ready (DDSR) Bit 1 Bit 1 Bit 9
ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1
Scratch Register (Note 4) Divisor Latch (LS) Divisor Latch (MS)
SCR DDL DLM
*DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
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Table 32- Register Summary for an Individual UART Channel (continued) BIT 2 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) BIT 3 Data Bit 3 Data Bit 3 Enable MODEM Status Interrupt (EMSI) BIT 4 Data Bit 4 Data Bit 4 0 BIT 5 Data Bit 5 Data Bit 5 0 BIT 6 Data Bit 6 Data Bit 6 0 BIT 7 Data Bit 7 Data Bit 7 0
Interrupt ID Bit Interrupt ID Bit 0 (Note 5) XMIT FIFO Reset Number of Stop Bits (STB) OUT1 (Note 3) Parity Error (PE) DMA Mode Select (Note 6) Parity Enable (PEN) OUT2 (Note 3) Framing Error (FE) Reserved
0
Reserved
FIFOs Enabled (Note 5) RCVR Trigger LSB Set Break
FIFOs Enabled (Note 5) RCVR Trigger MSB Divisor Latch Access Bit (DLAB) 0
Even Parity Select (EPS) Loop Break Interrupt (BI)
Stick Parity
0 Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13
0
Transmitter Error in RCVR Empty (TEMT) FIFO (Note 5) (Note 2) Ring Indicator (RI) Bit 6 Bit 6 Bit 14 Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10
Delta Data Carrier Detect (DDCD) Bit 3 Bit 3 Bit 11
Clear to Send (CTS) Bit 4 Bit 4 Bit 12
Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7: The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x1D).
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6.5.6
NOTES ON SERIAL PORT OPERATION
FIFO Mode Operation GENERAL The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. TX AND RX FIFO Operation The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have the Tx FIFO empties after this condition, the Tx been loaded into the FIFO, concurrently. When interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud).
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6.6
Infrared Interface
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Several IR implementations have been provided for the second UART in this chip (logical device 5), IrDA, and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins. These can be selected through the configuration registers. IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform. The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform. If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. The following figure shows the block diagram of the IR components in the LPC47S45x:
ACE Registers COM Host Interface ACE UART Sharp ASK IrDA SIR Output MUX IR COM
IR Options Register, Bit 6
6.6.1
IR TRANSMIT PIN
The following description pertains to the IRTX pin of the LPC47S45x. Following a VTR POR, the IRTX pin will be output and low. It will remain low until one of the following conditions are met: GP53/TXD2/IRTX Pin. This pin defaults to the GPIO function. 1. This pin will remain low following a VCC POR until the IRTX function is selected for the pin AND serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IRCC block (if IR is enabled through the IR Option Register for Serial Port 2). This pin will remain low following a VCC POR until the TXD2 function is selected for the pin AND serial port 2 is enabled by setting the activate bit, at which the pin will reflect the state of the transmit output of serial port 2 (if COM is enabled through the IR Option Register for Serial Port 2). This pin will remain low following a VCC POR until the corresponding GPIO data bit (GP5 register bit 3) is set or the polarity bit in the GP53 control register is set.
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3.
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6.7
Parallel Port
The LPC47S45x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The LPC47S45x also provides a mode for support of the floppy disk controller on the parallel port. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 The bit map of these registers is: D0 D1 D2 D3 DATA PORT PD0 PD1 PD2 PD3 TMOUT 0 0 nERR STATUS PORT STROBE AUTOFD nINIT SLC CONTROL PORT PD0 PD1 PD2 PD3 EPP ADDR PORT PD0 PD1 PD2 PD3 EPP DATA PORT 0 PD0 PD1 PD2 PD3 EPP DATA PORT 1 PD0 PD1 PD2 PD3 EPP DATA PORT 2 PD0 PD1 PD2 PD3 EPP DATA PORT 3 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4 D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5 D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 PD7 nBUSY 0 PD7 PD7 PD7 PD7 PD7 Note 1 1 1 2 2 2 2 2 BASE ADDRESS + 00H BASE ADDRESS + 01H BASE ADDRESS + 02H BASE ADDRESS + 03H BASE ADDRESS + 04H BASE ADDRESS + 05H BASE ADDRESS + 06H BASE ADDRESS + 07H
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Table 33 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. PIN NUMBER 83 68-75 80 79 78 77 82 81 66 67 STANDARD nSTROBE PD<0:7> nACK BUSY PE SLCT nALF nERROR nINIT nSLCTIN EPP nWrite PData<0:7> Intr nWait (User Defined) (User Defined) NDatastb (User Defined) nRESET NAddrstrb ECP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse(3) Select nAutoFd, HostAck(3) nFault(1) nPeriphRequest(3) nInit(1) nReverseRqst(3) nSelectIn(1,3)
6.7.1
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
Data Port ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU. Status Port ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of a read cycle. The bits of the Status Port are defined as follows: BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect. BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has been detected. BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected.
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BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. BIT 6 nACK - nACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character. Control Port ADDRESS OFFSET = 02H The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written. EPP Address Port ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP mode. EPP Data Port 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during
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which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode. EPP Data Port 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP Data Port 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP Data Port 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
6.7.2
EPP 1.9 OPERATION
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e. a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated. EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.
Write Sequence of operation: 1. 2. 3. 4. The host initiates an I/O write cycle to the selected EPP register. If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid.
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5. 6.
7. 8.
Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no more wait states are required followed by the TAR to complete the write cycle. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.
Read Sequence of Operation: 1. 2. 3. 4. 5. 6. 7. The host initiates an I/O read cycle to the selected EPP register. If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip tri-states the PData bus and deasserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. Peripheral drives PData bus valid. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. a) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase. b) The chip drives the sync that indicates that no more wait states are required and drives valid data onto the LAD[3:0} signals, followed by the TAR to complete the read cycle. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
8. 9.
6.7.3
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read. EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation: 1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE.
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2. 3. 4. 5. 6. 7.
The host initiates an I/O write cycle to the selected EPP register. The chip places address or data on PData bus. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a timeout occurs. The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data bus for the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation: 1. 2. 3. 4. 5. 6. 7. 8. 9. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. The host initiates an I/O read cycle to the selected EPP register. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a time-out occurs. The Peripheral drives PData bus valid. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. The chip drives the final sync and deasserts nDATASTB or nADDRSTRB. Peripheral tri-states the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 34 - EPP Pin Descriptions EPP SIGNAL nWRITE PD<0:7> INTR WAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE O I/O I I EPP DESCRIPTION This signal is active low. It denotes a write operation. Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP). This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. It is used to denote data read or write operation. This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. It is used to denote address read or write operation. Same as SPP mode. Same as SPP mode. Same as SPP mode.
DATASTB RESET ADDRSTB PE SLCT nERR
nData Strobe nReset nAddress Strobe Paper End Printer Selected Status Error
O O O I I I
Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low.
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6.7.4
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer capability.
6.7.5
VOCABULARY
The following terms are used in this document: assert: forward: reverse: Pword: 1 0 When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. Host to Peripheral communication. Peripheral to Host communication A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8 bits. A high level. A low level.
These terms may be considered synonymous: PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is: D7 PD7 Addr/RLE nBusy 0 D6 PD6 nAck 0 D4 D3 D2 D1 D0 PD4 PD3 PD2 PD1 PD0 Address or RLE field PError Select nFault 0 0 0 Direction ackIntEn SelectIn nInit autofd strobe Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 1 0 0 0 0 Parallel Port IRQ Parallel Port DMA nErrIntrEn dmaEn serviceIntr full empty D5 PD5 Note 2 1 1 2 2 2
data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
0 0 compress intrValue MODE
Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration Registers.
6.7.6
ECP IMPLEMENTATION STANDARD
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. Description
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The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. Table 35 - ECP Pin Descriptions NAME nStrobe PData 7:0 nAck PeriphAck (Busy) TYPE O I/O I I DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode.
PError (nAckReverse)
I
Select nAutoFd (HostAck)
I O
nFault (nPeriphRequest)
I
nInit
O
nSelectIn
O
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined. Table 36 - ECP Register Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr ADDRESS (Note 1) +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. Table 37 - Mode Descriptions MODE 000 001 010 011 100 101 110 111 DESCRIPTION* SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) Reserved Test mode Configuration mode
*Refer to ECR Register Description Data And ecpAFifo Port ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is ony defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet .
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Device Status Register (DSR) ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register. Device Control Register (DCR) ADDRESS OFFSET = 02H The Control Register is located at an offset of '02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). BITS 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction.
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ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again. The full and empty bits always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! BIT 6 intrValue Returns the value of the interrupt to determine possible conflicts. BITS [5:3] Parallel Port IRQ (read-only) Refer to Table 38B. BITS [2:0] Parallel Port DMA (read-only) Refer to Table 38C.
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ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is 0). 0: Disables DMA unconditionally. BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt. case dmaEn=1: During DMA (this bit is set to a 1 when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data. Table 38A - Extended Control Register R/W 000: MODE Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).
001:
010:
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R/W 011:
100: 101: 110: 111:
MODE ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register L3-CRF0. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull).
Table 38B CONFIG REG B IRQ SELECTED BITS 5:3 15 110 14 101 11 100 10 011 9 010 7 001 5 111 All Others 000 Operation Mode Switching/Software Control
DMA SELECTED
Table 38C CONFIG REG B BITS 2:0 3 011 2 010 1 001 All Others 000
Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above. ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: Set Set Set Set Direction = 0, enabling the drivers. strobe = 0, causing the nStrobe signal to default to the deasserted state. autoCAD = 0, causing the nAutoFd signal to default to the deasserted state. mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively.
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Note: all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty. ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 39 - Channel Commands Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) D7 0 1 D[6:0] Run-Length Count (0-127) (mode 0011 0X00 only) Channel Address (0-127)
Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided. Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes. LPC Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals.
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Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 serviceIntr = 0 Disables the DMA and all of the service interrupts. Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold.
An interrupt is generated when: 1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received. 2. For Programmed I/O: a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. b. When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO. 3. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. 4. When ackIntEn is 1 and the nAck signal transitions from a low to a high. FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by encoding the LDRQ# pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host intiating a DMA cycle for the requested channel, and addresses need not be valid. An interrupt is generated when a TC cycle is received. (Note: The only way to properly terminate DMA transfers is with a TC cycle.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP stop requesting DMA cycles when the FIFO becomes empty or when a TC cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting DMA
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cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and serviceIntr has been re-enabled. Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same. Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold =(16-) data bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16) bytes may be read from the FIFO in a single burst. Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16-) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to . (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO.
6.7.7
PARALLEL PORT FLOPPY DISK CONTROLLER
The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in the Parallel Port Mode Register, as defined in the Parallel Port Mode Register, Logical Device 3, at 0xF1. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins. The following parallel port pins are read as follows by a read of the parallel port register: 1. 2. 3. Data Register (read) = last Data Register (write) Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1 Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1
The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive select register: 1. 2. nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1. If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is selected.
The FDC signals are muxed onto the Parallel Port pins as shown in Table 41.
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For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port function independently of the state of the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the multiplexed FDD interface functions normally regardless of the Parallel Port Power control, CR22.3. Table 40 illustrates this functionality. Table 40 - Modified Parallel Port FDD Control PARALLEL PORT FDC PARALLEL PORT PARALLEL PORT FDC STATE STATE CONTROL CR22.3 LD3:CRF1.1 LD3:CRF1.0 1 0 0 OFF ON 0 0 0 OFF OFF X 1 X ON OFF X 1 (Note1) 1 Note : The Parallel Port Control register reads as "Cable Not Connected" when the Parallel Port FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1. PARALLEL PORT POWER Table 41 - FDC Parallel Port Pins CONNECTOR QFP PIN DIRECTION PIN # CHIP PIN # SPP MODE 1 83 nSTROBE I/O 2 68 PD0 I/O 3 69 PD1 I/O 4 70 PD2 I/O 5 71 PD3 I/O 6 72 PD4 I/O 7 73 PD5 I/O 8 74 PD6 I/O 9 75 PD7 I/O 10 80 nACK I 11 79 BUSY I 12 78 PE I 13 77 SLCT I 14 82 nALF I/O 15 81 nERROR I 16 66 nINIT I/O 17 67 nSLCTIN I/O Note 1: These pins are outputs in mode PPFD2, inputs in mode PPFD1. FDC MODE (nDS0) nINDEX nTRK0 nWP nRDATA nDSKCHG (nMTR0) nDS1 nMTR1 nWDATA nWGATE DRVDEN0 nHDSEL nDIR nSTEP PIN DIRECTION I/(O) Note1 I I I I I I/(O) Note1 O O O O O O O O
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6.8
Power Management
Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown. Note: For additional power management capabilities see the following sections: LPC Interface, subsection 6.3.2 Power Management on page 26. Real Time Clock, subsection 6.9.9 Power Management on page 104. 8042 Keyboard Controller Description, subsection 6.11.3 Keyboard Power Management on page 110 ACPI/PME/SMI Features on page 147
6.8.1
FDC POWER MANAGEMENT
Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B0. When set, this bit allows FDC to enter powerdown when all of the following conditions have been met: 1. 2. 3. 4. The motor enable pins of register 3F2H are inactive (zero). The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts). The head unload timer must have expired. The Auto powerdown timer (10msec) must have timed out.
An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met. Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown. Note: At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating environment is such that this delay cannot be guaranteed, the auto powerdown mode should not be used and Direct powerdown mode should be used instead. The Direct powerdown mode requires at least 8us delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the internal microcontroller can prepare itself to accept commands. DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective. Wake Up From Auto Powerdown If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the PCI_RESET# pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part: 1. 2. 3. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part). A read from the MSR register. A read or write to the Data register.
Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied. Register Behavior
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Table 42 illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 42 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it. Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access has been completed. Pin Behavior The LPC47S45x is specifically designed for systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the LPC47S45x can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part. Table 42 - PC/AT and PS/2 Available Registers AVAILABLE REGISTERS BASE + ADDRESS PC-AT PS/2 (MODEL 30) ACCESS PERMITTED Access to these registers DOES NOT wake up the part 00H ---SRA R 01H ---SRB R 02H DOR (1) DOR (1) R/W 03H ------04H DSR (1) DSR (1) W 06H ------07H DIR DIR R 07H CCR CCR W Access to these registers wakes up the part 04H MSR MSR R 05H Data Data R/W Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part. System Interface Pins Table 43 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Table 43 - State of System Pins in Auto Powerdown SYSTEM PINS LAD[3:0] LDRQ# LPCPD# LFRAME# PCI_RESET# PCI_CLK SER_IRQ FDD Interface Pins
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STATE IN AUTO POWERDOWN Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged
DATASHEET
All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 44 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 44 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA nWRTPRT nTRK0 nINDEX nDSKCHG nMTR0 nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL DRVDEN[0:1] STATE IN AUTO POWERDOWN INPUT PINS Input Input Input Input Input OUTPUT PINS Tristated Tristated Active Active Tristated Tristated Active Active
6.8.2
UART POWER MANAGEMENT
Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. management operations: 1. 2. When set, these bits allow the following auto power
The transmitter enters auto powerdown when the transmit buffer and shift register are empty. The receiver enters powerdown when the following conditions are all met: A. Receive FIFO is empty B. The receiver is waiting for a start bit. While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes.
Note:
Exit Auto Powerdown The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes state.
6.8.3
PARALLEL PORT
Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used. The EPP logic is in powerdown under any of the following conditions: 1. EPP is not enabled in the configuration registers. 2. EPP is not selected through ecr while in ECP mode. The ECP logic is in powerdown under any of the following conditions: 1. ECP is not enabled in the configuration registers. 2. SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. Exit Auto Powerdown
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The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers.
6.9
Real Time Clock
The Real Time Clock Supercell (RTC) is a complete time of day clock with alarm, day of month alarm, one hundred year calendar, a century byte, and a programmable periodic interrupt. The RTC address space consists of two-128 byte banks of CMOS RAM (Bank0 and Bank1.) Each bank is accessible via address and data ports. These access ports have relocatable addresses and are accessible by the CPU. The 128 bytes of Bank0 contain the following: eleven registers of time, calendar, century, and alarm data, four control and status registers, and 112 bytes of general-purpose registers. The 128 bytes of Bank1 contain general-purpose registers.
Features: Allow 32kHz-clock input or a 32kHz crystal. Counts seconds, minutes, and hours of the day. Counts days of the week, date, month and year. Binary or BCD representation of time, calendar and alarm. 24-hour daily alarm. 30-day alarm. RTC/CMOS Bank Addresses are relocatable. The RTC CMOS Bank0 index register (70h) is shadowed RTC power source is switched internally between the VTR and VBAT pins according to VTR_PWRGD Lockable CMOS Ram Address Ranges. Polarity selection on IRQ8
6.9.1
CONFIGURATION REGISTERS
The RTC configuration registers, in Logical Device Number 0x06, provide activation control and the base address for the run-time registers (See Table 45) The activate bit register 0x30, Bit D0 enables RTC/CMOS Bank0. The activate bit register 0x30, Bit D1 enables RTC/CMOS Bank1. Table 45 - RTC Configuration Registers INDEX 0x30 TYPE R/W PCI RESET 0x00 SOFT RESET 0x00 VCC POR 0x00 VTR POR 0x00 D7 D6 D5 Activate RESERVED DESCRIPTION D4 D3 D2 D1 Activate CMOS Bank1 D0
0x60
R/W
0x00
0x00
0x00
0x00
0x61 0x62
R/W R/W
0x70 0x00
0x70 0x00
0x70 0x00
0x00 0x00
0x63 0x70
R/W R/W
0x74 0x00
0x74 0x00
0x74 0x00
0x00 0x00
Activate RTC/ CMOS Bank0 RTC/CMOS Bank0 Primary Base Address High Byte "0" "0" "0" "0" A9 A8 A1 A1 1 0 RTC/CMOS Bank0 Primary Base Address Low Byte A7 A6 A5 A4 A3 A2 A1 "0" Note CMOS Bank1 Primary Base Address High Byte "0" "0" "0" "0" A9 A8 A1 A1 1 0 CMOS Bank1 Primary Base Address Low Byte A7 A6 A5 A4 A3 A2 A1 "0" Note Primary Interrupt Select (Note 1)
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INDEX 0xF0
TYPE R/W
PCI RESET 0x00
SOFT RESET -
VCC POR 0x00
VTR POR 0x00
0xF1 R Note: This is a read/write bit that is ignored. Note 1: The polarity of IRQ8 is programmable via bit 0 of register 0xF1 in Logical Device A.
DESCRIPTION D7 D6 D5 D4 D3 D2 D1 D0 Bank 1: Bit[0] = 1 : Lock CMOS RAM 0 - 1Fh Bit[1] = 1 : Lock CMOS RAM 20 - 3Fh Bit[2] = 1 : Lock CMOS RAM 40 - 5Fh Bit[3] = 1 : Lock CMOS RAM 60 - 7Fh Bit[7:4] Reserved, set to "0" Once set, bit[3:0] can not be cleared by a write; bits[3:0] are cleared on VCC Power On Reset, VCC Power Off, or upon a PCI Reset. Once lock bits are set, the Host is locked out of accessing the locked locations as long as VCC is active. When VCC goes to 0V, the lock bits are cleared. Shadow of RTC/CMOS Bank 0 Index register
6.9.2
HOST I/O INTERFACE
Each bank has a CMOS Address Register and a CMOS Data Register. Each bank's CMOS Address Register is located at the corresponding base address setup by the Configuration Registers in Table 45. Each bank's CMOS Data Register is located at an offset of the corresponding base (see Table 46.) Bit D7 of both CMOS Address Registers is not used for the CMOS RAM address decoding. All four CMOS Run Time registers are fully read/write. Table 46 - CMOS Run time Registers HOST ADDRESS* Bank0 * (W) (note 1) Bank0 * + 1(R/W) Bank1 * (R/W) Bank1 * + 1(R/W) BANK RTC/CMOS Bank0 RTC/CMOS Bank0 CMOS Bank1 CMOS Bank1 FUNCTION CMOS Address Register CMOS Data Register CMOS Address Register CMOS Data Register
Note 1: CMOS Address Register for Bank0 is a write only register at this address. The contents of this register are readable in the configuration register section. (see Table 45 - RTC CONFIGURATION R)
6.9.3
INTERNAL REGISTERS
Table 47 shows the address map of the RTC and CMOS RAM, eleven registers of time, calendar, century, and alarm data, four control and status registers, and 241 bytes of CMOS registers Table 47 - RTC and CMOS RAM Address Map BANK Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0 Bank0
SMSC DS - LPC47S45x
BASE OFFSET 0 1 2 3 4 5 6 7 8 9 A B
REGISTER TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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REGISTER FUNCTION Register 0: Seconds Register 1: Seconds Alarm Register 2: Minutes Register 3: Minutes Alarm Register 4: Hours Register 5: Hours Alarm Register 6: Day of Week Register 7: Day of Month Register 8: Month Register 9: Year Register A: Register B: (Bit 0 is Read Only)
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DATASHEET
BANK Bank0 Bank0 Bank0 Bank0
BASE OFFSET C D 32 E-31, 33-7F
REGISTER TYPE R R/W R/W R/W
REGISTER FUNCTION Register C: Register D: Day of Month Alarm Century Byte General purpose
All 256 bytes are directly writable and readable by the host with the following exceptions: Registers C is read only Bit 7 of Register D is read only which can only be set by a read of Register D. Bit 6 of Register D is read only . Bit 7 of Register A is read only Bits 0 of Register B is read only
6.9.4
TIME CALENDAR AND ALARM
The processor program obtains time and calendar information by reading the appropriate locations. The program may initialize the time, calendar and alarm by writing to these locations. The contents of the twelve time, calendar and alarm registers can be in binary or BCD as shown in Table 48 - RTC Register Valid Range. Before initializing the internal registers, the SET bit in Register B should be set to a "1" to prevent time/calendar updates from occurring. The program initializes the twelve locations in the binary or BCD format as defined by the DM bit in Register B. The SET bit may then be cleared to allow updates. The 12/24 bit in Register B establishes whether the hour locations represent 1 to 12 or 0 to 23. The 12/24 bit cannot be changed without reinitializing the hour locations. When the 12 hour format is selected, the high order bit of the hours byte represents PM when it is a "1". Once per second, the twelve time, calendar and alarm registers are updated, Incrementing by one second and checking for an alarm condition. During the update cycle all the registers in Table 48, except Register D, are not accessible by the processor program. The update cycle time is shown in Table 49. The update logic contains circuitry for automatic end-of-month recognition as well as automatic leap year compensation. The three alarm registers may be used in two ways. First, when the program inserts an alarm time in the appropriate hours, minutes and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second usage is to insert a "don't care" state in one or more of three alarms registers. The "don't care" code is any hexadecimal byte from C0 to FF inclusive. That is the two most significant bits of each byte, when set to "1" create a "don't care" situation. An alarm interrupt each hour is created with a "don't care" code in the hours alarm location. Similarly, an alarm is generated every minute with "don't care" codes in the hours and minutes alarm bytes. The "don't care" codes in all three alarm bytes create an interrupt every second. Table 48 - RTC Register Valid Range ADD 0 1 2 3 4 REGISTER FUNCTION Register 0: Seconds Register 1: Seconds Alarm Register 2: Minutes Register 3: Minutes Alarm Register 4: Hours (12 hour mode) (24 hour mode) Register 5: Hours Alarm (12 hour mode) (24 hour mode)
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5
BCD RANGE 00-59 00-59 00-59 00-59 01-12 am 81-92 pm 00-23 01-12 am 81-92 pm 00-23
BINARY RANGE 00-3B 00-3B 00-3B 00-3B 01-0C 81-8C 00-17 01-0C 81-8C 00-17
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DATASHEET
ADD 6 7 8 9 D 32
REGISTER FUNCTION Register 6: Day of Week Register 7: Day of Month Register 8: Month Register 9: Year Day of Month Alarm Century Byte
BCD RANGE 01-07 01-31 01-12 00-99 01-31 00-39
BINARY RANGE 01-07 01-1F 01-0C 00-63 01-1F 00-3F
6.9.5
UPDATE CYCLE
An update cycle is executed once per second if the SET bit in Register B is clear and the DV0-DV2 divider is not clear. The SET bit in the "1" state permits the program to initialize the time and calendar registers by stopping an existing update and preventing a new one from occurring. The primary function of the update cycle is to increment the seconds register, check for overflow, increment the minutes register when appropriate and so forth through to the year of the century byte. The update cycle also compares each alarm register with the corresponding time register and issues an alarm if a match or if a "don't care" code is present. The length of an update cycle is shown in Table 49. During the update cycle the time, calendar and alarm registers are not accessible by the processor program. If the processor reads these locations before the update cycle is complete, the output will be undefined. The UIP (update in progress) status bit is set during the interval. When the UIP bit goes high, the update cycle will begin 244 s later. Therefore, if a low is read on the UIP bit the user has at least 244 s before time/calendar data will be changed. Table 49 - RTC Update Cycle Timing INPUT CLOCK FREQUENCY 32.768 kHz 32.768 KHZ UPDATE CYCLE TIME 1948 s MINIMUM TIME BEFORE START OF UPDATE CYCLE 244 s
UIP BIT 1 0
6.9.6
CONTROL AND STATUS REGISTERS
The RTC has four registers, which are accessible to the processor program at all times, even during the update cycle. Register A B7 UIP B6 DV2 B5 DV1 B4 DV0 B3 RS3 B2 RS2 B1 RS1 B0 RS0
UIP The update in progress bit is a status flag that may be monitored by the program. When UIP is a "1" the update cycle is in progress or will soon begin. When UIP is a "0" the update cycle is not in progress and will not be for at least 244 s. The time, calendar, and alarm information is fully available to the program when the UIP bit is "0". The UIP bit is a read only bit and is not affected by VTR POR. Writing the SET bit in Register B to a "1" inhibits any update cycle and then clears the UIP status bit. DV2-0 Three bits are used to permit the program to select various conditions of the 22 stage divider chain. Table 50 shows the allowable combinations. The divider selection bits are also used to reset the divider chain. When the time/calendar is first initialized, the program may start the divider chain at the precise time stored in the registers. When the divider reset is removed, the first update begins one-half second later. These three read/write bits are not affected by VTR POR.
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Table 50 - RTC Divider Selection Bits OSCILLATOR FREQUENCY 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz REGISTER A BITS DV2 DV1 DV0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 X 1 1 X
MODE Normal Operate Reset Divider Normal Operate Test Test Reset Divider
RS3-0 The four rate selection bits select one of 15 taps on the divider chain or disable the divider output. The selected tap determines rate or frequency of the periodic interrupt. The program may enable or disable the interrupt with the PIE bit in Register B. Table 51 lists the periodic interrupt rates and equivalent output frequencies that may be chosen with the RS0-RS3 bits. These four bits are read/write bits that are not affected by VTR POR. Table 51 - RTC Periodic Interrupt Rates RATE SELECT RS3 RS2 RS1 RS0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 32.768 kHz TIME BASE PERIOD RATE FREQUENCY OF INTERRUPT OF INTERRUPT 0.0 3.90625 ms 256 Hz 7.8125 ms 128 Hz 8.192 Hz 122.070 s 244.141 s 488.281 s 976.562 s 1.953125 ms 3.90625 ms 7.8125 ms 15.625 ms 31.25 ms 62.5 ms 125 ms 250 ms 500 ms 4.096 kHz 2.048 kHz 1.024 kHz 512 Hz 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz
0100 0101 0110 0 1 1 1 1 1 1 1 1 Register B B7 SET B6 PIE B5 AIE 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1
B4 UIE
B3 RES
B2 DM
B1 24/12
B0 DSE
SET When the SET bit is a "0", the update functions normally by advancing the counts once-per-second. When the SET bit is a "1", an update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the middle of initialization. SET is a read/write bit, which is not modified by VTR POR or any internal functions. PIE The periodic interrupt enable bit is a read/write bit which allows the periodic-interrupt flag (PF) bit in Register C to cause the IRQB port to be driven low. The program writes a "1" to the PIE bit in order to receive periodic interrupts at
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the rate specified by the RS3 - RS0 bits in Register A. A "0" in PIE blocks IRQB from being initiated by a periodic interrupt, but the periodic flag (PF) is still set at the periodic rate. PIE is not modified by any internal function, but is cleared to "0" by a VTR POR. AIE The alarm interrupt enable bit is a read/write bit, which when set to a "1" permits the alarm flag (AF) bit in Register C to assert IRQB. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes (including a "don't care" alarm code of binary 11XXXXXX). When the AIE bit is a "0", the AF bit does not initiate an IRQB signal. The VTR POR port clears AIE to "0". The AIE bit is not affected by any internal functions. UIE The update-ended interrupt enable bit is a read/write bit which enables the update-end flag (UF) bit in Register C to assert IRQB. The VTR POR port or the SET bit going high clears the UIE bit. RES Reserved - read as zero DM The data mode bit indicates whether time and calendar updates are to use binary or BCD Formats: The DM bit is written by the processor program and may be read by the program, but is not modified by any internal functions or by VTR POR. A "1" in DM signifies binary data, while a "0" in DM specifies BCD data. 24/12 The 24/12 control bit establishes the format of the hours byte as either the 24 hour mode if set to a "1", or the 12 hour mode if cleared to a "0". This read/write bit is not affected by VTR POR or any internal function. DSE The daylight savings enable bit is read only and is always set to a "0" to indicate that the daylight savings time option is not available. Register C REGISTER C IS A READ ONLY REGISTER B7 IRQF B6 PF B5 AF B4 UF B3 0 B2 0 B1 0 B0 0
IRQF The interrupt request flag is set to a "1" when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 Any time the IRQF bit is a "1", the IRQB signal is driven low. All flag bits are cleared after Register C is read or by the VTR POR port. PF The periodic interrupt flag is a read only bit which is set to a "1" when a particular edge is detected on the selected tap of the divider chain. The RS3 -RS0 bits establish the periodic rate. PF is set to a "1" independent of the state of the PIE bit. PF being a "1" sets the IRQF bit and initiates an IRQB signal when PIE is also a "1". The PF bit is cleared by VTR POR or by a read of Register C. AF The alarm interrupt flag when set to a "1" indicates that the current time has matched the alarm time. A "1" in AF causes a "1"to appear in IRQF and the IRQB port to go low when the AIE bit is also a "1". A VTR POR or a read of Register C clears the AF bit. UF The update-ended interrupt flag bit is set after each update cycle. When the UIE bit is also a "1", the "1" in UF causes the IRQF bit to be set and asserts IRQB. A VTR POR or a read of Register C causes UF to be cleared. b3-0 The unused bits of Register C are read as "0" and cannot be written.
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Register D MSB b7 VRT LSB B0
b6 0
b5
b4
b3 b2 Day of month
b1
VRT The Valid RAM and Time (VRT) bit is cleared by the RTC to indicate that both the main power (VTR) and the battery power (VBAT) are both low at the same time. This is the only case where the contents of the RAM, as well as, the time and calendar registers are not valid. The VRT bit can only be set by a read of Register D. The Host can set the VRT bit reading Register D after PWRGD =1. b6 Read as zero and cannot be written. b5:b0 Day of month Alarm; these bits store the day of month alarm value. If set to 000000b, then a don't care state is assumed. The host must configure the Day of month alarm for these bits to do anything, yet they can be written at any time. If the Day of month alarm is not enabled, these bits will return zeros. These bits are not affected by PCI_RESET, VTR_POR or VCC_POR. The BCD Range for the Day of month of month alarm is 1-31 and the Binary Range is 01-1F. Century Byte The century byte is located at RTC/Bank0 register 0x32. The century byte is incremented by one when the year byte changes from 99 or 0x63 to 0. The BCD Range for the century byte is 00-39 and the Binary Range is 00h-3Fh. General Purpose Registers 0xEh-0x7FH, except 0x32 (The Century Byte) in Bank0 and 0x0-0x7F in Bank1 are general-purpose "CMOS" registers. These registers can be used by the host and are fully available during the time update cycle. The contents of these registers are preserved by Vbat power. Registers Eh-7Fh are in bank0 and registers 80h-FFh are in bank1.
6.9.7
INTERRUPTS
The RTC includes three separate fully automatic sources of interrupts to the processor. The alarm interrupt may be programmed to occur at rates from one-per-second to one-a-day. The periodic interrupt may be selected for rates from half-a-second to 122.070 s. The update-ended interrupt may be used to indicate to the program that an update cycle is completed. Each of these independent interrupts are described in greater detail in other sections. The processor program selects which interrupts, if any, it wishes to receive by writing a "1" to the appropriate enable bits in Register B. A "0" in an enable bit prohibits the IRQB port from being asserted due to that interrupt cause. When an interrupt event occurs a flag bit is set to a "1" in Register C, which are set independent of the state of the corresponding enable bits in Register B. Each of the three interrupt sources have separate flag bits in Register C. The flag bits may be used with or without enabling the corresponding enable bits. The flag bits in Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included in Register C to ensure the bits that are set are stable throughout the read cycle. All bits which are high when read by the program are cleared, and new interrupts are held until after the read cycle. If an interrupt flag is already set when the interrupt becomes enabled, the IRQB port is immediately activated, though the interrupt initiating the event may have occurred much earlier. When an interrupt flag bit is set and the corresponding interrupt-enable bit is also set, the IRQB port is driven low. IRQB is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a "1" whenever the IRQB port is being driven low. The serial interrupt that is used for the RTC interrupt is selected through register 0x70 of Logical Device 6. The polarity of IRQ8 is programmable via bit 0 of register 0xF1 in Logical Device A. Frequency Divider The RTC has 22 binary divider stages following the clock input. The output of the divider is a one Hertz signal to the update-cycle logic. The divider is controlled by the three divider bits (DV2-DV0) in Register A. As shown in Table 50 the divider control bits can select the operating mode, or be used to hold the divider chain reset that allows precision
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setting of the time. When the divider chain is changed from reset to the operating mode, the first update cycle is one-half second later. Periodic Interrupt Selection The periodic interrupt allows the IRQB port to be triggered from once every 500 ms to once every 122.07 s. As Table 51 shows, the periodic interrupt is selected with the RS0-RS3 bits in Register A. The periodic interrupt is enabled with the PIE bit in Register B.
6.9.8
32KHZ CLOCK INPUT
The XOSEL pin is used to select either a 32.768kHz input clock or a 32.768kHz crystal to drive the Real Time Clock Interface). When XOSEL = `0', the RTC uses a 32.768kHz crystal connected between the XTAL1 and XTAL2 pins. When XOSEL = `1', the RTC is driven by a 32.768kHz single-ended clock source connected to the XTAL2 pin. Note: Standby current on Vbat is <1A.
6.9.9
POWER MANAGEMENT
The RTC and CMOS RAM utilize VBAT power plane. The VTR POR does not affect the clock, calendar, or RAM functions. When VTR POR is active, the following occurs: Periodic Interrupt Enable (PIE) is cleared to "0". Alarm Interrupt Enable (AIE) bit is cleared to "0". Update Ended Interrupt Enable (UIE) bit is cleared to "0". Update Ended Interrupt Flag (UF) bit is cleared to "0". Interrupt Request status Flag (IRQF) bit is cleared to "0". Periodic Interrupt Flag (PIF) is cleared to "0". The RTC and CMOS registers are not accessible. Alarm Interrupt Flag (AF) is cleared to "0". RTC IRQ is not enabled If both the main power (VTR) and the battery power (VBAT) are both low at the same time and then re-applied (i.e. a new battery is installed) the following occurs: Initialize all registers 00-0D to a "00" when VTR is applied. The oscillator is disabled immediately. The VRT bit is cleared to "0". When PWRGD = 0, all host inputs are locked out so that the internal registers cannot be modified by the host system. The Host lockout condition continues for 500usec (min) to 1msec (max) after PWRGD =1. The Host lockout condition does not occur when either of the following occurs: RTC Divider Selection mode is not in normal mode in Table 50. The VRT bit in Register D is a "0".
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6.10 Serial IRQ
The LPC47S45x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
6.10.1 TIMING DIAGRAMS FOR SER_IRQ CYCLE
A) Start Frame timing with source sampled a low pulse on IRQ1
SL
or
START FRAME H R T
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME S R T S R T S R T
H PCI_CLK SER_IRQ Drive Source
IRQ
START
1
Host Controller
None
IRQ1
None
Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. B) Stop Frame Timing with Host using 17 SER_IRQ sampling period
IRQ14 FRAME SRT PCI_CLK SER_IRQ Driver None
IRQ15 FRAME SRT
IOCHCK# FRAME SRT
STOP FRAME
NEXT CYCLE T
I
2
H
R
STOP1 IRQ15 None Host Controller
START 3
Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle Note 1: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. Note 2: There may be none, one or more Idle states during the Stop Frame. Note 3: The next SER_IRQ cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. SER_IRQ Cycle Control There are two modes of operation for the SER_IRQ Start Frame. 1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ is immediately tri-stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. Any SER_IRQ Device (i.e., The LPC47S45x) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle.
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2.
Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every Stop Frame.
An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle's mode. SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47S45x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the LPC47S45x drives the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SER_IRQ is left tri-stated. During the Recovery phase the LPC47S45x drives the SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase the LPC47S45x tri-states the SER_IRQ. The LPC47S45x will drive the SER_IRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse). SER_IRQ Sampling Periods SIGNAL SAMPLED Not Used IRQ1 nIO_SMI/IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
SER_IRQ PERIOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
# OF CLOCKS PAST START 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47
The SER_IRQ data frame will now supports IRQ2 from a logical device on Period 3, which can also be used for the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2. SER_IRQ Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2) and 7 (KBD) shall have IRQ13 as a choice for their primary interrupt. The polarity of IRQ8 is programmable via bit 0 of register 0xF1 in Logical Device A. The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the SMI pin via bit 7 of the SMI Enable Register 2. Stop Cycle Control
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Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame's low time is two clocks then the next SER_IRQ Cycle's sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. If the Stop Frame's low time is three clocks then the next SER_IRQ Cycle's sampled mode is the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. Latency Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. EOI/ISR Read Latency Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of order. AC/DC Specification Issue All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state. Reset and Initialization The SER_IRQ bus uses PCI_RESET# as its reset signal. The SER_IRQ pin is tri-stated by all agents while PCI_RESET# is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system's IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller's responsibility to provide the default values to 8259's and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes.
6.10.2 ROUTABLE IRQ TO SERIAL IRQ CONVERSION CAPABILITY
IRQINx functions are on pins 61 (IRQINA), 62 (IRQINB), 40 (IRQINC) and 44 (IRQIND) and are muxed onto the GPIO pins as inputs. The IRQINx pin's IRQ time slot in the Serial IRQ stream is selected via a 4-bit control register for each IRQINx function. A value of 0000 disables the IRQ function. These pins are implemented such that internal functions take precedence over the IRQIN pins, i.e. if the IRQIN control register is set to 0x06 and the internal floppy is set to 0x06, the floppy alone will drive the Serial IRQ stream in the IRQ6 time slot. See Configuration registers located at an offset 0xF4 and 0xF5 in Logical Device A. User Note: In order to use an IRQ for one of the IRQINx inputs that are muxed on the GPIO pins, the corresponding IRQ must not be used for any of the devices in the LPC47S45x.
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6.11 8042 Keyboard Controller Description
The LPC47S45x is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the LPC47S45x enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of the 8042" in the 8-Bit Embedded Controller Handbook.
8042A
P27 P10 P26 TST0 P23 TST1 P22 P11
LS05 KDAT KCLK MCLK MDAT
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the LPC47S45x.
6.11.1 KEYBOARD INTERFACE
The LPC47S45x LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output Data register. Table 52 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs. Table 52 - I/O Address Map ADDRESS 0x60 0x64 COMMAND Write Read Write Read BLOCK KDATA KDATA KDCTL KDCTL FUNCTION (NOTE 1) Keyboard Data Write (C/D=0) Keyboard Data Read Keyboard Command Write (C/D=1) Keyboard Status Read
Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read. Keyboard Data Write This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set. Keyboard Data Read This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software.
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Keyboard Command Write This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set. Keyboard Status Read This is an 8 bit read only register. Refer to the description of the Status Register for more information. CPU-to-Host Communication The LPC47S45x CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 53. Table 53 - Host Interface Flags 8042 INSTRUCTION OUT DBB Host-to-CPU Communication The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets the register contents as a command. When bit 3 is "0", the CPU interprets the register contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. KIRQ If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the LPC47S45x CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.) If "EN FLAGS" has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ low; a high forces KIRQ high. MIRQ If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the LPC47S45x CPU has read the DBB register. If "EN FLAGS" has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support). Gate A20 A general purpose P21 is used as a software controlled Gate A20 or user defined output. 8042 PINS The 8042 functions P17, P16 and P12 are implemented as in a true 8042 part. Reference the 8042 spec for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within 2030nsec. After 500nsec (six 8042 clocks) the port enable goes away and the external pull-up maintains the output signal as 1. In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external pull-up can pull the pin high, and the pin can be shared. In 8042 mode, the pins cannot be programmed as input nor inverted through the GP configuration registers. FLAG Set OBF, and, if enabled, the KIRQ output signal goes high
6.11.2 EXTERNAL KEYBOARD AND MOUSE INTERFACE
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system
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expansion, the LPC47S45x provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. The LPC47S45x has four high-drive, open-drain output, bidirectional port pins that can be used for external serial interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to P11. NOTE: External pull-ups may be required.
6.11.3 KEYBOARD POWER MANAGEMENT
The keyboard provides support for two power-saving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power down mode the clock to the 8042 is stopped. Soft Power Down Mode This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and program execution starts from program memory location 0. Hard Power Down Mode This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above.
6.11.4 INTERRUPTS
The LPC47S45x provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
6.11.5 MEMORY CONFIGURATIONS
The LPC47S45x provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
6.11.6 REGISTER DEFINITIONS
Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information. Host I/F Status Register The Status register is 8 bits wide. Table 54 shows the contents of the Status register. Table 54 - Status Register D7 UD Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47S45x CPU. UD C/D Writable by LPC47S45x CPU. These bits are user-definable. (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the LPC47S45x CPU's nIBF (MIRQ) interrupt if enabled. When the LPC47S45x CPU
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D6 UD
D5 UD
D4 UD
D3 C/D
D2 UD
D1 IBF
D0 OBF
IBF
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reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal. OBF (Output Buffer Full) - This flag is set to whenever the LPC47S45x CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset.
6.11.7 EXTERNAL CLOCK SIGNAL
The LPC47S45x Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.
6.11.8 DEFAULT RESET CONDITIONS
The LPC47S45x has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 55 for the effect of each type of reset on the internal registers. Table 55 - Resets DESCRIPTION KCLK KDAT MCLK MDAT Host I/F Data Reg Host I/F Status Reg N/A: Not Applicable GATEA20 And Keyboard Reset The LPC47S45x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. Port 92 Fast GATEA20 and Keyboard Reset Port 92 Register This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device 7, 0xF0) set to 1. This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions. NAME LOCATION DEFAULT VALUE ATTRIBUTE SIZE Port 92 92h 24h Read/Write 8 bits HARDWARE RESET (PCI_RESET#) Low Low Low Low N/A 00H
BIT 7:6 5 4 3 2 1
PORT 92 REGISTER FUNCTION Reserved. Returns 00 when read Reserved. Returns a 1 when read Reserved. Returns a 0 when read Reserved. Returns a 0 when read Reserved. Returns a 1 when read ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.
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BIT 0
PORT 92 REGISTER FUNCTION Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse active (low) for a minimum of 1 s after a delay of 500 ns. Before another nALT_RST pulse can be generated, this bit must be written back to a 0. nGATEA20 8042 P21 0 0 1 1 ALT_A20 0 1 0 1 System nA20M 0 1 1 1
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND'ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6s, after a delay of a minimum of 14s. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0). If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92 Register and this pulse is AND'ed with the pulse generated from the 8042. This pulse is output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration.
14us
~ ~
6us
8042
P20
KRST
KBDRST P92 Bit 0 KRST_GA20 Bit 2 nALT_RST Pulse Gen
14us
Note: When Port 92 is disabled, writes are ignored and reads return undefined values.
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR'ed with the A20GATE signal from the keyboard controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low.
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~ ~
6us
6.11.9 LATCHES ON KEYBOARD AND MOUSE IRQS
The implementation of the latches on the keyboard and mouse interrupts is shown below.
KLATCH Bit
VCC D KINT Q
KINT
new
8042
CLR
RD 60
FIGURE 2 - KEYBOARD LATCH
MLATCH Bit
VCC
D Q CLR
MINT new
MINT
8042
RD 60
FIGURE 3 - MOUSE LATCH
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The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0. These bits are defined as follows: Bit[4]: MLATCH - Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default), 1=MINT is the latched 8042 MINT. Bit[3]: KLATCH - Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default), 1=KINT is the latched 8042 KINT. See the Configuration section for description on these registers.
6.11.10 KEYBOARD AND MOUSE PME GENERATION
The LPC47S45x sets the associated PME Status bits when the following conditions occur: Keyboard Interrupt Mouse Interrupt Active Edge on Keyboard Data Signal (KDAT) Active Edge on Mouse Data Signal (MDAT) These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global PME_EN bit are set. Refer to the PME Support section for more details on the PME interface logic and refer to the Runtime Register section for details on the PME Status and Enable registers. The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC. The keyboard data and mouse data PMEs can be generated both when the part is powered by VCC, and when the part is powered by VTR (VCC=0). When using the keyboard and mouse for wakeup, it may be necessary to isolate the keyboard and mouse signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is due to the fact that the normal operation of the 8042 can prevent the system from entering or exiting a sleep state or trigger false PME events. The LPC47S45x has "isolation" bits for the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but block the keyboard clock and data signals and the mouse clock and data signals from the 8042. These bits may be used when it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state. See the SMSC Application Note titled "Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O Parts" for more information. The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device 7, Register 0xF0 (KRST_GA20) and are defined as follows: Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal to the mouse wakeup (PME) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal to the keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon exiting the sleep state. If either of the isolation bits is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this may produce undesired results. It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go inactive (S1, S2).
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6.12 General Purpose I/O
The LPC47S45x provides a set of flexible Input/Output control functions to the system designer through the 55 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME.
6.12.1 GPIO PINS
The following pins include GPIO functionality. These pins are defined in the table below.
Table 56 - GPIO Pin Functionality REGISTER DEFAULT ON VTR POR Input Input Input REGISTER DEFAULT ON VCC POR GPIO Function SMI/PME FUNCTIONALITY
PIN 6 7 20 31 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 57 58 64 65 66 67 95 97 98 99 100 101
NAME
POWER WELL
GP40 /DRVDEN0 GP41 /DRVDEN1 GP42 /IO_PME# GP43 /DDRC GP80 GP81 GP82 GP83 GP84 GP85 GP86 GP87 GP62 /IRQINC GP20 /P17 /DS1# GP21 /P16 GP22 /P12 / MTR1# GP23 /IRQIND GP24 /P17 GP25 /P12 GP26 SYSOPT GP60 /LED1 GP61 /LED2 GP27 /IO_SMI# GP30 /nXCS2 GP31 /nXCS3 GP32 /FAN_TACH GP33 /FAN GP34 /IRQINA GP35 /IRQINB GP36 /nKBDRST GP37 /A20M GP50 /RI2# GP51 /DCD2# GP52 /RXD2 /IRRX GP53 /TXD2 /IRTX GP54 /DSR2# GP55 /RTS2# /SADR0
VCC VCC (Note 1) VTR VCC (Note 1) VCC VCC VCC VCC VCC VCC VCC VCC VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VTR (Note 1) VTR (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VTR (Note 1) VCC (Note 1) VCC (Note 1)
PME/SMI IO_PME# PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI /IO_SMI# PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI
Rev. 04-30-07
Input Output,low Output, low Output, low Output, low Output, high Output, high Output, high Output, high Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output, low Input Input
Output, low Output, low -
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PIN 102 103 107 108 109 110 111 112 113 114 116 117 118 119 120 121 122 123
NAME
POWER WELL
GP56 /CTS2# GP57 /DTR2# /SADR1 nXWR/GP70 nXRD/GP71 XA0/GP72 XA1/GP73 XA2/GP74 XA3/GP75 nXCS0/GP76 XCS1/GP77 XD0/GP10 XD1/GP11 XD2/GP12 XD3/GP13 XD4/GP14 XD5/GP15 XD6/GP16 XD7/GP17
VCC (Note 1) VCC (Note 1) VCC VCC VCC VCC VCC VCC VCC VCC VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1) VCC (Note 1)
REGISTER DEFAULT ON VTR POR Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input
REGISTER DEFAULT ON VCC POR -
SMI/PME FUNCTIONALITY
PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI PME/SMI
Note 1: These pins have input buffers into the wakeup logic that are powered by VTR.
6.12.2 DESCRIPTION
Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP8. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are located in either the Runtime Register block (see the Runtime Registers section) or in Logical Device A (Runtime Registers) located in the Configuration Register block (see the Configuration section). The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 57.
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Table 57 - General Purpose I/O Port Assignments
PIN NO. /QFP DEFAULT FUNCTION ALT. FUNCTION 1 ALT. FUNCTION 2 ALT. FUNCTION 3 DATA 1 REGISTER DATA REG BIT NO. REG OFFSET (HEX)
116 117 118 119 120 121 122 123 44 45 46 47 48 49 50 53 54 55 57 58 64 65 66 67 6 7 20
X-Bus Data 0 X-Bus Data 1 X-Bus Data 2 X-Bus Data 3 X-Bus Data 4 X-Bus Data 5 X-Bus Data 6 X-Bus Data 7 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO P17 P16 P12 IRQ Input D P17 P12 IO_SMI# X-Bus Chip Select 2 X-Bus Chip Select 3 Fan Tachometer Fan Control IRQ Input A IRQ Input B Keyboard Reset Gate A20 Drive Density Select 0 Drive Density Select 1 Power Management Event Device Disable Reg. Control Drive Select 1 EETI Motor On 1
GP1
0 1 2 3 4 5 6 7
4B
GP2
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2
4C
EETI
GP3
4D
GP4 EETI
4E
31 N/A N/A N/A N/A 95
GPIO Reserved Reserved Reserved Reserved GPIO
EETI
3 4 5 6 7 0
Ring Indicator 2
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PIN NO. /QFP
DEFAULT FUNCTION
ALT. FUNCTION 1
ALT. FUNCTION 2
ALT. FUNCTION 3
DATA 1 REGISTER
DATA REG BIT NO.
REG OFFSET (HEX)
97 98 99 100 101 102 103
GPIO GPIO GPIO GPIO GPIO GPIO GPIO
GP6 50 51 GPIO EETI 0 52 GPIO EETI 1 43 GPIO 2 N/A Reserved 3 N/A Reserved 4 N/A Reserved 5 N/A Reserved 6 N/A Reserved 7 GP7 51 107 nXWR GPIO 0 108 nXRD GPIO 1 109 XA0 GPIO 2 110 XA1 GPIO 3 111 XA2 GPIO 4 112 XA3 GPIO 5 113 nXCS0 GPIO 6 114 XCS1 GPIO 7 GP8 4A 35 GPIO 0 36 GPIO 1 37 GPIO 2 38 GPIO 3 39 GPIO 4 40 GPIO 5 41 GPIO 6 42 GPIO 7 Note 1: The GPIO Data and Configuration Registers are located in PME block at the offset shown from the RUNTIME REGISTERS BLOCK address.
Data Carrier Detect 2 Receive Serial Data 2 Transmit Serial Data 2 Data Set Ready 2 Request to Send 2 Clear to Send 2 Date Terminal Ready 2 LED1 LED2 IRQINC
1 Infrared Rx Infrared Tx 2 3 4 5 6 7
6.12.3 GPIO CONTROL
Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the "Runtime Registers" section or the "Configuration Registers" section in Logical Device A of this specification. Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7] determines the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO functions and the nSMI Alternate functions. The Polarity Bit (bit 1) of the GPIO control registers control the GPIO pin when the pin is configured for the GPIO function and when the pin is configured for the alternate function for all pins, with the exception of the DDRC function on GP43 and the either edge triggered interrupts.
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The basic GPIO configuration options are summarized in Table 58.
Table 58 - GPIO Configuration Summary SELECTED FUNCTION DIRECTION BIT POLARITY BIT DESCRIPTION
GPIO
B0 0 0 1 1
B1 0 1 0 1
Pin is a non-inverted output. Pin is an inverted output. Pin is a non-inverted input. Pin is an inverted input.
6.12.4 GPIO OPERATION
The operation of the GPIO ports is illustrated in FIGURE 4.
Note: FIGURE 4 is for illustration purposes only and in not intended to suggest specific implementation details.
GPIO Configuration Register bit-1 (Polarity) GPIO Configuration Register bit-0 (Input/Output)
SD-bit GPx_nIOW
D-TYPE D Q
Transparent
0 1
Q
GPx_nIOR
D
GPIO PIN
GPIO Data Register Bit-n
FIGURE 4 - GPIO FUNCTION ILLUSTRATION Note: When the following functions are selected, the associated GPIO pins have bi-directional functionality: P12, P16, P17.
When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect (Table 59). When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the last value written to the data register (Table 59).
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Table 59 - GPIO Read/Write Behavior HOST OPERATION Read Write GPIO INPUT PORT Latched Value Of Gpio Pin No Effect GPIO OUTPUT PORT Last Write To GPIO Data Register Bit Placed In GPIO Data Register
The LPC47S45x provides 37 GPIOs that can directly generate a PME. See the table in the next section. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in the PME_STS2 - PME_STS7 registers. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN 2 - PME_EN7 registers and the PME_EN bit in the PME_EN register is set, a PME will be generated. These registers are located in the Runtime Registers Block, which are located at the address contained in the configuration registers 0x60 and 0x61 in Logical Device A. The PME status bits for the GPIOs are cleared on a write of `1'. In addition, the LPC47S45x provides 36 GPIOs that can directly generate an SMI. See the table in the next section.
Note: PME events can also be generated by the PM1 and GPE status registers. GP23, GP34, GP35, and GP[50:57] can generate a PME event if they are enabled in either the PME enable registers or the GPE enable registers. See section 7 ACPI/PME/SMI Features on page 147 for a detailed description of the ACPI specific registers, PM1 and GPE.
6.12.5 GPIO PME AND SMI FUNCTIONALITY
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP10-GP17 GP20-GP27 GP30-GP37 GP41, GP43 GP50-GP57 GP60, GP61, GP62 This following is the list of PME status and enable registers for their corresponding GPIOs: PME_STS2 and PME_EN2 for GP10-GP17 PME_STS3 and PME_EN3 for GP20-GP27 PME_STS4 and PME_EN4 for GP30-GP33, GP41, GP43, GP60, GP61 PME_STS5 and PME_EN5 for GP50-GP57 PME_STS7 and PME_EN7 for GP34-GP37, GP62 The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable registers. GP10-GP17 GP20-22, GP24-27 GP30-GP37 GP41, GP43 GP50-GP57 GP60, GP61, GP62 The following SMI status and enable registers for these GPIOs: SMI_STS3 and SMI_EN3 for GP20-22, GP24-27, GP60 SMI_STS4 and SMI_EN4 for GP30-GP33, GP41, GP43, GP61 SMI_STS5 and SMI_EN5 for GP50-GP57 SMI_STS5 and SMI_EN5 for GP10-GP17 SMI_STS7 and SMI_EN7 for GP34-GP37, GP62 The following GPIOs have "either edge triggered interrupt" (EETI) input capability. These GPIOs can generate a PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in the MSC_STS status register that is set on both edges. The corresponding bits in the PME and SMI status registers are also set on both edges.
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GP21, GP22 GP41, GP43 GP60, GP61 The following table summarizes the PME and SMI functionality for each GPIO. It also shows the Either Edge Triggered Interrupt (EETI) input capability for the GPIOs and the power source for the buffer on the I/O pads.
GPIO PME SMI EETI OUTPUT BUFFER POWER VCC VCC VCC VCC VCC VCC VCC VTR VCC VCC VCC VCC VCC VCC VCC NOTES
GP10-GP17 GP20-22, GP24-GP26 GP23 GP27 GP30-GP37 GP40 GP41 GP42 GP43 GP50-GP57 GP60 GP61 GP62 GP70-GP77 GP80-GP87
Yes Yes Yes Yes Yes No Yes No/IO_PME# Yes Yes Yes Yes Yes No No
Yes Yes No Yes/IO_SMI# Yes No Yes No Yes Yes Yes Yes Yes No No
No GP21-GP22 No No No No Yes No Yes No Yes Yes No No No
5 2 1
3 4
1 1
Note 1: GP40, GP[70:77], and GP[80:87] should not be connected to any VTR powered external circuitry. These pins do not have input buffers into the wakeup logic, therefore they cannot be used for wakeup. Note 2: The GP33 pin cannot be used for wakeup to generate a PME while the part is under VTR power (VCC=0) since GP33 is the FAN pin which comes up as output and low on a VCC POR and PCI Reset. This pin reverts to its non-inverting GPIO output function when VCC is removed from the part. Note 3: GP43 defaults to the GPIO function on VCC POR and PCI Reset. Note 4: GP53 pin cannot be used for wakeup to generate a PME while the part is under VTR power (VCC=0) since GP53 is the IRTX pin which comes up as output and low on a VTR POR, VCC POR and PCI Reset. This pin is a noninverting GPIO output (low) when VCC is removed from the part. Note 5: Since GP27 can be used to generate an SMI and as the IO_SMI# output, do not enable GP27 to generate an SMI (by setting bit 7 of the SMI Enable Register 3) if the IO_SMI# function is selected on the GP27 pin. Use GP27 to generate an SMI event only if the SMI output is enabled on the Serial IRQ stream.
6.12.6 EITHER EDGE TRIGGERED INTERRUPTS
Six GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then the bits that control input/output, polarity and open collector/push-pull have no effect on the function of the pin. However, the polarity bit does affect the value of the GP bit (i.e., register GP2, bit 2 for GP22). A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function is selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are cleared on a write of `1'. There are also status bits for the EETIs located in the MSC_STS register, which are also cleared on a write of `1'. The MSC_STS register provides the status of all of the EETI interrupts within one register. The PME, SMI or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is selected for the pin. Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits. Status bits are cleared on a write of `1'. See Runtime Register section for more information.
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6.12.7 LED FUNCTIONALITY
The LPC47S45x provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D and 0x5E from the base address located in the primary base I/O address in Logical Device A. The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed. In order to control an LED while the part is under VTR power, the GPIO pin must be configured for the LED function and either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking current to control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to blink the LED under VTR power. The LED will not blink under VTR power (VCC removed) if an external 32kHz clock source is not connected. The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is powered by either VCC or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current from VTR even when VCC is present. The LED control registers are defined in the "Runtime Register" section.
6.13 Watch Dog Timer
The LPC47S45x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an interrupt through the WDT_CFG Runtime Register. The LPC47S45x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are selected via bit[7] of the WDT_TIMEOUT register (Runtime Register at offset 0x52). The WDT time-out value is set through the WDT_VAL Runtime register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Runtime register. Note: Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU. There are three system events which can reset the WDT. These are a Keyboard Interrupt, a Mouse Interrupt, or I/O reads/writes to address 0x201. The effect on the WDT for each of these system events may be individually enabled or disabled through bits in the WDT_CFG Runtime register. When a system event is enabled through the WDT_CFG register, the occurrence of that event will cause the WDT to reload the value stored in WDT_VAL and reset the WDT time-out status bit if set. If all three system events are disabled the WDT will inevitably time out. The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the Time-out status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Runtime register. When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status bit. The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out) Runtime register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watch Dog Status). Bit 2 of the WDT_CTRL is self-clearing. See the Runtime Registers section for description of these registers.
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6.14 Power On Elapsed Timer (POET)
The LPC47S45x is equipped with two counters to monitor the length of time VCC and VTR are active. Each counter clocks one second per LSBit. The one second clock input to the counter is derived from the 32.768 KHz clock input(i.e. CLKI32). This input is powered by VCC and maintained by VTR when VCC is removed. The counter values are maintained in the Runtime Register section and are accessible by either the LPC Bus or SMBus. When the value is read from the register, all 32 bits are latched to avoid the value being updated during a read. Latching of these bytes will not effect the continued counting of the counter. The only time the counter is reset is on a Vbat POR or when the counter reaches its' maximum value of FFFFFFFFh, It is unlikely that the counter will ever reach its' maximum, since it would take in excess of 136 years for the 32 bit counter to reach its' maximum. These counters may be accessed by the LPC bus through the Runtime Registers at offsets 6Dh to 74h or by the SMBus in the SMBus2 Registers at offsets 04h to 0Bh. Since the counters are read-only, no arbitration is necessary between the LPC Bus and the SMBus. See Table 60 - Runtime Register Block Summary - Power On Elapsed Time Counters. The counter registers will map into the SMBus 8-bit registers address field for SMBus Read access as described in section 6.18.4 SMBus2 Register Summary on page 139.
6.14.1 VCC POWER ON ELAPSED TIME COUNTER
In the Runtime Register Block, at offsets 6Dh through 70h, a 4 byte counter is used to indicate power on elapsed time for Vcc. The counter is powered by VCC and is enabled by Vcc PWRGD. It should be noted that the counter value is maintain by Vbat and therefore may only be reset by Vbat POR as shown in Table 60. When Byte 1 (LSB) is read, by the LPC Bus or SMBus, Bytes 2 through 4 are latched for eventual read. It is required the counter (Bytes 1 through 4) be read LSB to MSB. Latching of bytes for read output will not affect continued counting.
6.14.2 VTR POWER ON ELAPSED TIME COUNTER
In the Runtime Register Block, at offsets 71h through 74h, a 4 byte counter is used to indicate power on elapsed time for Vtr. The counter is powered by Vtr and is enabled by Vtr PWRGD as shown in Table 60. When Byte 1 (LSB) is read, by the LPC Bus or SMBus, Bytes 2 through 4 are latched for eventual read. It is required the counter (Bytes 1 through 4) be read LSB to MSB. Latching of bytes for read output will not affect continued counting.
Table 60 - Runtime Register Block Summary - Power On Elapsed Time Counters OFFS ET (HEX) 6D TYPE PCI RESET VCC POR VTR POR VBAT POR SOFT RESET REGISTER SMBUS2 REG OFFSET 04
R R R R R R R R
-
-
-
0X00 0X00 0X00 0X00 0X00 0X00 0X00 0X00
-
Vcc_CNT1 Byte 1 (LSB) Vcc_CNT2 Byte 2 Vcc_CNT3 Byte 3 Vcc_CNT4 Byte 4 (MSB) Vtr_CNT1 Byte 1 (LSB) Vtr_CNT2 Byte 2 Vtr_CNT3 Byte 3 Vtr_CNT4 Byte 4 (MSB)
6E 6F 70 71 72 73 74
05 06 07 08 09 0A 0B
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6.15 Fan Speed Control And Monitoring
The LPC47M45x may control the speed of one fan as well as monitor it if it is equipped with a fan tachometer output. The following sections will clarify how this chip controls the speed of a fan and its' monitoring capabilities.
6.15.1 FAN SPEED CONTROL
The fan speed control for the LPC47M45x is implemented as pulse width modulators with fan clock speed selection. There is one signal pin, FAN (located on pin 58), dedicated to controlling the speeds of a fan. This signal is controlled by the Runtime registers FAN and Fan Control that are described below (see also section 8 Runtime Registers on page 156 ).
Note: The fan control pin comes up as an output and is low following a VCC POR and PCI Reset. This pin may not be used for wakeup events under VTR power (VCC=0).
Fan Speed Control Summary The following table illustrates the different modes for the fan.
Table 61 - Different Modes for Fan FAN CLOCK CONTROL BIT (NOTE 1) FAN CLOCK MULTIPLIER BIT (NOTE 2) FAN CLOCK SOURCE SELECT BIT (NOTE 3) X 0 0 1 1 0 0 1 1 X FAN CLOCK SELECT BIT (NOTE 4) 6-BIT DUTY CYCLE CONTROL BITS[6:1] (DCC)
FOUT
DUTY CYCLE (%)
0 0 0 0 0 0 0 0 0 1
Note 1: Note 2: Note 3: Note 4:
X 0 0 0 0 1 1 1 1 X
X 0 1 0 1 0 1 0 1 X
0Hz - LOW 15.625kHz 23.438kHz 40Hz 60Hz 31.25kHz 46.876kHz 80Hz 120Hz 0Hz - HIGH
0 1-63
(DCC/64) 100
-
-
This is FAN Register Bit 0 This is Fan Control Register Bit 2 This is Fan Control Register Bit 0 This is FAN Register Bit 7
FAN Register The FAN Register is located at 0x56 from base I/O in Logical Device A. The bits are defined below. See the register description in the "Runtime Registers" section.
Fan Clock Select Bit, D7 The Fan Clock select bit in the FAN registers is used with the Fan Clock Source Select and the Fan Clock Multiplier bits in the Fan Control register to determine the fan speed FOUT. See Table 61 above. Duty Cycle Control for Fan, Bits D6 - D1 The Duty Cycle Control (DCC) bits determine the fan duty cycle. The LPC47M45x has 1.56% duty cycle resolution. When DCC = "000000" (min. value), FOUT is always low. When DCC is "111111" (max. value), FOUT is almost always high; i.e., high for 63/64th and low for 1/64th of the FOUT period. Generally, the FOUT duty cycle (%) is (DCC / 64) x 100. Fan Clock Control, Bit D0 The Fan Clock Control bit D0 is used to override the Duty Cycle Control for Fan bits and force FOUT always high. When D0 = "0", the DCC bits determine the FOUT duty cycle. When D0 = 1, FOUT is always high, regardless of the state of the DCC bits.
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Fan Control Register The Fan Control Register is located at 0x58 from base I/O in Logical Device A. The bits are defined below. See the register description in the "Runtime Registers" section.
Fan Count Divisor, Bits D5-D4 Fan Count Divisor bit in Fan Control Register is used to determine fan tachometer count. The choices for the divisor are 1, 2, 4 and 8. See "Fan Tachometer Input" section. Fan Clock Multiplier, Bit D2 The Fan Clock Multiplier bit is used with the Fan Clock Source Select bit in the Fan Control Register and the Fan Clock Select bit in Fan register to determine the FOUT. When the Fan Clock Multiplier bit = "0", no clock multiplier is used. When the Fan Clock Multiplier bit = "1", the clock speed determined by the Fan Clock Source Select bit is doubled. Fan Clock Source Select, Bit D0 The Fan Clock Source Select and the Fan Clock Multiplier bits in the Fan Control register are used with the Fan Clock Select bit in the Fan register to determine the fan speed FOUT. See Table 61 above.
6.15.2 FAN SPEED MONITORING
The LPC47M45x monitors the speed of the fan by utilizing fan tachometer input signal from fans equipped with tachometer outputs. There is a signal pin dedicated to the fan tachometer input (pin 57) which is monitored by using the Fan Tachometer register. This signal, as well as the Fan Tachometer register, are described below (see also section 6.17.2 Runtime Registers on page 129). Fan Tachometer Input The fan tachometer input is used to measure the speed at which the fan is rotating. The fan tachometer input is a train of square pulses with a 50% duty cycle (see FIGURE 5) that are derived from the magnetic fields generated by the rotating rotor of the fan. The speed of the fan can be determined by calculating the period of the Fan Tachometer input pulse.
Note: All calculations are based on fans that emit 2 square pulses per revolution.
TR Fan Tachometer Input TR = Revolution Time = 60/RPM (sec) TP = Pulse Time = T /2 R (Two Pulses Per Revolution) F = 32.786kHz / Divisor
TP Clock Source for Counter
FIGURE 5 - FAN TACHOMETER INPUT AND CLOCK SOURCE
The counter is used to determine the period of the Fan Tachometer input pulse. This counter, if reset on the rising edge of the fan tachometer input pulse, measures the number of clock pulses generated by the clock source for the duration of one fan tachometer input pulse. Since two fan tachometer input pulses are generated per revolution of the fan rotor, the speed of the fan is easily calculated. Everytime the fan tachometer input resets the counter, it also latches the value of the counter into the Fan Tachometer register. This value is used by the operating system to monitor the speed of the fan. Fan Monitoring Logic The clock source for the counter is the output of the programmable divider whose input is the 32.768kHz oscillator (see FIGURE 6). The counter is reset by the rising edge of each fan tachometer input pulse, by itself if it reaches its' maximum count of 0xFF, or by writing to the preload register.
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If the fan is functioning, a value is preloaded into the counter on the rising edge of the Fan Tachometer input. The counter counts the number of clock pulses generated for the duration of one Fan Tachometer input pulse. This value (Count) is then stored into the FAN_TACH register. If the fan is operating at 70% (or less) of the maximum capacity, the Count value will be greater than or equal to 192 and thereby generate a PME# signal. To ensure the FAN_TACH register has been updated if the fan suddenly seizes, a second PME is generated when the counter reaches 0xFF and the FAN_TACH register is latched again. The FAN_TACH register will remain at this value until another Fan Tachometer input pulse is received. A representation of the logic for the fan tachometer implementation is shown below.
Preload
32kHz
Programmable Divider 1, 2, 4, 8
Counter Logic to generate PME event Latch Fan Tach Register on Fan Tach input pulse or Counter=0xFF
Note: If the fan is working the FAN_TACH register will be latched by the Fan Tachometer input. If the fan fails, the first time the overflow bit is generated the FAN_TACH register will be updated. The Fan_Tach Registerwill not be updated again until after the Fan Tachometer input resets the counter.
FIGURE 6 - CONCEPTUAL BLOCK DIAGRAM OF FAN MONITORING LOGIC
Fan Tachometer Register The Fan Tachometer register, referred to as FAN_TACH, is used to store the value of the counter that monitors the speed of the fan. This value may be used by the operating system to monitor how the fan is functioning. The ACPI BIOS polls this register periodically to determine the speed at which the fan rotor is revolving. See the Metalious ACPI/Manageability Specification, v1.0, dated April 30, 1999. The BIOS looks for particular values in this register to determine the rate at which the fan is functioning. (i.e. Count = FFh; means the fan has stopped). Since the count value must correspond to a particular rate of functioning, the Preload register is used to offset any differences. Therefore, the equation below has been derived to calculate the desired values for Count. The fan count is determined according to the following equation: Count = 1 2 x 1.966 x 106 RPM x Divisor (Term 1) + Preload (Equation 1)
In addition to the ACPI BIOS polling the register, a PME or SMI is generated at a count of 192, if enabled through the PME or SMI enable register, which corresponds to the "upper limit" for the fan count. This value is made to correspond to the "lower limit" of the RPM for the fan by programming the divisor and preload value accordingly. Typical practice is to consider 70% of normal RPM a fan failure. Fan Preload Register The preload value is programmable via the FAN Preload Register. The preload is the initial value for the fan count, which is used to adjust the count such that the value of 192 corresponds to the "lower limit" of the RPM. By setting the preload value and divisor properly, a PME or SMI will be generated when the RPM reaches the percentage of the nominal RPM that indicates a fan failure.
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Notice in the examples shown below the Preload value was determined to be 32 for a fan that normally operates at 4400 RPMs. This preload value was determined for the case that a PME should be initiated at 70% of normal operation. A PME is generated when the counter reaches 192, but at 70% in this example only 160 counts are generated during one Fan Tachometer input pulse leaving a difference of 32. Examples Term 1 in the equation above is 1/2 of the value determined by multiplying the clock source of 32.768kHz by 60sec/min and dividing by the product of the revolutions per minute times the divisor. The factor of 1/2 in Term 1 corresponds to two pulses per revolution. The default divisor, located in the Fan Control Register, is two. This results in a value for Term 1 in Equation 1 of 111.70 (~112) for a 4400 RPM. The following tables show examples of the desired functionality.
Note: All calculations of Count were based on tachometer inputs with two pulses per revolution and on the clock source input divided down by two (default settings). TIME PER REVOLUTION TERM 1 FOR "DIVIDE BY 2" (DEFAULT) IN DECIMAL COUNT = (TERM 1) + PRELOAD 144 192 218 255 (maximum count)
RPM
PRELOAD
COMMENTS
4400 3080 2640 2204
13.64 ms 19.48 ms 22.73 ms 27.22 ms
112 counts 160 counts 186 counts 223 counts
32 32 32 32
Typical RPM 70% RPM 60% RPM 50% RPM
The divisor for each fan is programmable via the Fan Control Register, Logical Device 8, 0xFA. The choices for the divisor are 1, 2, 4 and 8. The default value is 2.
COUNTS FOR THE GIVEN SPEED IN DECIMAL 144 144 144 144
MODE SELECT
NOMINAL RPM
TIME PER REVOLUTION
PRELOAD
70% RPM
TIME PER REVOLUTION FOR 70% RPM
Divide by 1 Divide by 2 Divide by 4 Divide by 8
8800 4400 2200 1100
6.82 ms 13.64 ms 27.27 ms 54.54 ms
32 32 32 32
6160 3080 1540 770
9.74 ms 19.48 ms 38.96 ms 77.92 ms
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6.16 Device Disable Register
There are two Device Disable Registers located in the LPC47S45x. 1. 2. Device Disable Register located in the Runtime Register block at offset 0x22 (accessible by LPC interface only) SMBus2 Device Disable Register located in the SMBus2 Registers at offset 01h (accessible by SMBus2 only)
6.16.1 DEVICE DISABLE REGISTER (LPC ONLY)
The Device Disable Register is located in the PME register block at offset 0x22 from the Runtime Registers Block base I/O address in logical device A. Bits [3:7] are used to enable/disable the Floppy, Serial Ports, and/or Parallel Port and Bit[0] is used for Floppy Write Protect. As a security feature, this register's contents may be locked (i.e., Read-Only) by setting Bit[1] Register Lock bit high, which is only cleared on a VCC POR or a PCI Reset. Writes to this register may also be blocked when the GP43 pin is configured for the Device Disable Register Control function (GP43 configuration register bit 2 =1) and the GP43 pin is high. The control register for device disable register is defined in the "Runtime Registers" section and described below. GPIO Device Disable Register Control The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43 configuration register to `01', selects the DDRC function for the GP43 pin. When bits[3:2]=01 the GP43 pin is an input, with non-inverted polarity. Bits[3:2] cannot be cleared by writing to these bits; they are cleared by VTR POR, VCC POR and PCI Reset. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a VCC POR, PCI Reset or VTR POR. When Register Lock bit in the Device Disable is set to high regardless of the value of GP43 pin, all the bits in the Device Disable Register are Read Only until a VCC POR. When the DDRC function is selected for GP43, the Device Disable register is controlled by the value of the GP43 pin as follows: If the GP43 pin is high, the Device Disable Register at offset 22h is Read-Only. If the GP43 pin is low, the Device Disable Register at offset 22h is Read/Write. The Device Disable register has a Register Lock bit (bit 1) that is cleared on VTR POR, VCC POR and PCI Reset. It cannot be cleared by software writing to the bit. The Device Disable register is controlled by the Register Lock bit as follows: If the Register Lock bit is high, the Device Disable Register is Read-Only, If the Register Lock bit is low, the Device Disable Register has no effect (default) The following table shows two different means of making the DDRC register read only.
DDRC ENABLE (BIT 2 OF GP43 REG) X 0 1 1 DDRC PIN REGISTER LOCK BIT REGISTER STATE
X X 0 1
1 0 0 0
Read Only Read/Write Read/Write Read Only
6.16.2 SMBUS2 DEVICE DISABLE REGISTER (SMBUS2 ONLY)
This device disable register is located in the SMBus2 register block and is only accessible through the SMBus2. The functionality of this register is identical to the LPC device disable register, with the exception to the GP43 pin when it is configured for it's DDRC function. Asserting the DDRC function on the GP43 pin has no effect on the SMBus2 Device Disable Register. See SMBus2 Device Disable Control on page 140 for a more detailed description of this register. Note: Either device disable register is capable of disabling the Parallel Port, Serial Port 1, Serial Port 2, and the Floppy by setting the respective bits to `1'. For a device to be enabled, both device disable registers must be set the respective device bit to enabled. Once the register lock bit is set in either register the only way to reset a device disable bit to enabled is by a VCC POR or a PCI Reset.
Note: The Register Lock bit in each device disable register only effects the register it is located in. (i.e. If the LPC Device Disable Register is Read-only, the SMBus2 register may be Read/Write). Asserting the DDRC function on GP43 pin only effects the LPC Device Disable Register.
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6.17 SMBus Controller
The LPC47S45x supports SMBus. SMBus is a serial communication protocol between a computer host and its peripheral devices. It provides a simple, uniform and inexpensive way to connect peripheral devices to a single computer port. A single SMBus on a host can accommodate up to 125 peripheral devices.
For a description of the SMBus protocol, please refer to the System Management Bus Specification Revision 1.0, February 15, 1995, available from Intel Corporation. The LPC47S45x is equipped with two independent SMBus devices, each with its own slave address, that share the SCLK and SDAT pins. The device described in this section is a master/slave controller and is referred to in this document as the SMBus. The second device, referred to as SMBus2, is a slave only device used to access internal SMBus2 Registers and the I/O devices on the X-Bus. The SMBus2 device is described in a later section. The SMBus can assert both an nIO_PME and an nIO_SMI event when enabled and following an SMBus interrupt. Refer to registers PME_STS6, PME_EN6, SMI_STS2 and SMI_EN2 in the Runtime Registers section for more information. The SMBus implementation in the LPC47S45x has the following addtions over theAccess.bus: 1. 2. Added Timeout Error (TE) Bit, in D6 of the SMBus Status Register. Added Timeout Interrupt Enable Bit D4 in the SMBus Control register.
6.17.1 CONFIGURATION REGISTERS
See the configuration registers section for the SMBus Configuration Registers (Logical Device 0x0B).
6.17.2 RUNTIME REGISTERS
Overview The SMBus contains five registers: 1. 2. 3. 4. 5. Control Status Own Address Data Clock
The five SMBus registers occupy four addresses in the Host I/O space (Table 62). The Own Address register and the Clock register are used to initialize the SMBus controller. Normally these registers are written once following device reset. The other registers are used during actual data transmission/reception. The Data register performs all serial-toparallel interfacing. The Control/Status register contains status information required for bus access and/or monitoring. Descriptions of these registers follow in the sections below.
Table 62 - SMBus Runtime Registers ISA HOST INTERFACE HOST INDEX HOST TYPE SMBus Base Address W SMBus Base Address R SMBus Base Address + 1 R/W SMBus Base Address + 2 R/W
REGISTER NAME Control Status Own Address Data
Clock
SMBus Base Address + 3
R/W
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Control Register
Overview
The Control/Status register manages the SMBus operation and provides operational status (Table 63). Control/Status register is located at the SMBus Base Address.
The
The Control register is write-only and is located at the SMBus Base Address. The Control register provides register access control and control over SMBus signals. The read-only component of the SMBus Base Address is the Status register, described in the Status Register section, below.
Table 63 - SMBus Control/Status Register (SMBus/Base Address) CONTROL Type Bit Def Default Status Type Bit Def Default Bit 7 PINC D7 D6 D5 D4 D3 D2 W W W W W W PINC ES0 Reserved TIE ENI STA 0x00 on VTR POR, VCC POR, PCI RESET or SOFT RESET D7 D6 D5 D4 D3 D2 R R R R R R PIN TE STS BER LRB AAS 0x81 on VTR POR, VCC POR, PCI RESET or SOFT RESET D1 W STO D1 R LAB D0 W ACK D0 R nBB
Control register bit D7 is the Pending Interrupt Not Control bit. Writing the PINC bit to a logic `1' deasserts all Status register bits except for bit D0 nBB (Bus Busy). NOTE: the PINC bit has no affect on the nBB bit. The PINC bit is self-clearing. Writing this bit to a logic `0' has no effect.
Bit 6 ESO
Control register bit D6 is the Enable Serial Output control bit. ESO enables or disables the SMBus serial I/O. When ESO is `1', SMBus serial communication is enabled; communication with serial shift data register is enabled and the bits in the Status register are available for reading.
Bit 5
RESERVED
Bit 4 TIE
The Timeout Interrupt Enable and the ENI bits determine whether or not an interrupt is generated as a result of an SMBus timeout error. When the TIE bit is `1' and ENI is asserted, SMBus timeout errors will generate an interrupt. When TIE is `0', SMBus timeout errors will not generate interrupts, regardless of the state of ENI. The TIE bit does not affect the Timeout Error bit TE in the Status register.
Bit 3 ENI
This bit enables the internal SMBus interrupt, nINT, which is generated when the PIN bit is asserted (`0').
Bit 2 and Bit 1 STA and STO
These bits control the generation of the SMBus Start condition and transmission of slave address and R/nW bit, generation of repeated Start condition, and generation of the STOP condition (see Table 64). When transmitting the command code or data byte the STA and STO bits should bit set for NOP function.
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The following is an example of how to program these bits for the Write Byte protocol. To issue a start command: - load the data register with slave address - write to the control register to initiate a start condition (i.e., Bits[2:1] = 10) (see Note 1) - poll status register for a successful completed transaction (i.e., PIN bit = `0' and LRB bit = `1') - write NOP to the control register to prevent repeated start condition (i.e., Bits[2:1] = 00) To issue a command/data byte: - load data register with command/data byte (see Note 1) - poll status register for a successful completed transaction (i.e., PIN bit = `0' and LRB bit = `1') To issue a stop command: - write to the control register to initiate a stop condition (i.e., Bits[2:1] = 01) (see Note 1) - load the data register with dummy data (Note: This issues stop condition. ) (Note 1: ESO bit must be `1' to shift serial data onto SMBus)
Table 64 - Instruction Table for Serial Bus Control STA 1 STO 0 PRESENT MODE SLV/REC FUNCTION START OPERATION Transmit START+address, remain MST/TRM if R/nW=0; go to MST/REC if R/nW=1. Same as for SLV/REC Transmit STOP go to SLV/REC mode; Note 1
1 0 1 0
0 1 1 0
MST/TRM MST/REC; MST/TRM MST ANY
REPEAT START STOP READ; STOP WRITE DATA CHAINING NOP
Send STOP, START and address after last master frame without STOP sent; Note 2 No operation; Note 3
Note 1: In master receiver mode, the last byte must be terminated with ACK bit high (`negative acknowledge'). Note 2: If both STA and STO are set high simultaneously in master mode, a STOP condition followed by a START condition + address will be generated. This allows `chaining' of transmissions without relinquishing bus control. Note 3: All other STA and STO mode combinations not mentioned in Table 64 are NOPs. Bit 0 ACK
This bit must be set normally to logic "1". This causes the SMBus to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The bit is reset (to logic "0") when the SMBus controller is operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a negative acknowledge on the SMBus, which halts further transmission from the slave device. Status Register
Overview
The Status register, the read-only component of the SMBus Base Address, enables access to SMBus operational status information.
Bit 7 PIN
Pending Interrupt Not. This bit is a status flag which is used to synchronize serial communication and is set to logic "0" whenever the chip requires servicing. The PIN bit is normally read in polled applications to determine when an SMBus byte transmission/reception is completed. When acting as transmitter, PIN is set to logic "1" (inactive) each time the data register is written. In receiver mode, the PIN bit is automatically set to logic "1" each time the data register is read. After transmission or reception of one byte on the SMBus (nine clock pulses, including acknowledge) the PIN bit will be automatically reset to logic "0" (active) indicating a complete byte transmission/reception. When the PIN bit is subsequently set to logic "1" (inactive) all status bits will be reset to "0" on a BER (bus error) condition.
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In polled applications, the PIN bit is tested to determine when a serial transmission/reception has been completed. When the ENI bit (bit 4 of write-only section of the control/status register) is also set to logic "1" the hardware interrupt is enabled. In this case, the PI flag also triggers and internal interrupt (active low) via the nINT output each time PIN is reset to logic "0". When acting as a slave transmitter or slave receiver, while PIN = "0", the chip will suspend SMBus transmission by holding the SCLK line low until the PIN bit is set to logic "1" (inactive). This prevents further data from being transmitted or received until the current data byte in the data register has been read (when acting as slave receiver) or the next data byte is written to the data register (when acting as slave transmitter).
PIN Bit Summary The PIN bit can be used in polled applications to test when a serial transmission has been completed. When the ENI bit is also set, the PIN flag sets the internal interrupt via the nINT output. In transmitter mode, after successful transmission of one byte on the SMBus the PIN bit will be automatically reset to logic "0" (active) indicating a complete byte transmission. In transmitter mode, PIN is set to logic "1" (inactive) each time the data register is written. In receiver mode, PIN is set to logic "0" (inactive) on completion of each received byte. Subsequently, the SCLK line will be held low until PIN is set to logic "1". In receiver mode, when the data register is read, PIN is set to logic "1" (inactive). In slave receiver mode, an SMBus STOP condition will set PIN=0 (active). PIN=0 if a bus error (BER) or a timeout error (TE) occurs while the Timeout Interrupt Enable is asserted (TIE). Bit 6 TE
When the Timeout Error bit D6 is `1', an SMBus timeout error has occurred (see Section 0 SMBus Timeout). Timeout errors generate an interrupt if the TIE bit is asserted (see Section on Bit 4 TIE). If the TIE bit is asserted, timeout errors will assert the PIN bit. The TE bit is deasserted `0' whenever the PIN bit is deasserted (see Section on Bit 7 Pin).
Bit 5 STS
When in slave receiver mode, this flag is asserted when an externally generated STOP condition is detected (used only in slave receiver mode).
Bit 4 BER
Bus error; a misplaced START or STOP condition has been detected. Resets nBB (to logic "1"; inactive), sets PIN = "0" (active).
Bit 3 LRB/AD0
Last Received Bit or Address 0 (general call) bit. This status bit serves a dual function, and is valid only while PIN=0: LRB holds the value of the last received bit over the SMBus while AAS=0 (not addressed as slave). Normally this will be the value of the slave acknowledgment; thus checking for slave acknowledgment is done via testing of the LRB. ADO; when AAS = "1" (Addressed as slave condition) the SMBus controller has been addressed as a slave. Under this condition, this bit becomes the AD0 bit and will be set to logic "1" if the slave address received was the `general call' (00h) address, or logic "0" if it was the SMBus controller's own slave address.
Bit 2 AAS
Addressed As Slave bit. Valid only when PIN=0. When acting as slave receiver, this flag is set when an incoming address over the SMBus matches the value in own address register (shifted by one bit) or if the SMBus `general call' address (00h) has been received (`general call' is indicated when AD0 status bit is also set to logic "1").
Bit 1 LAB
Lost Arbitration Bit. This bit is set when, in multi-master operation, arbitration is lost to another master on the SMBus.
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Bit 0 nBB
Bus Busy bit. This is a read-only flag indicating when the SMBus is in use. A zero indicates that the bus is busy, and access is not possible. This bit is set/reset (logic "1"/logic "0") by Start/Stop conditions. Own Address Register When the chip is addressed as slave, this register must be loaded with the 7-bit SMBus address to which the chip is to respond. During initialization, the own address register must be written to, regardless whether it is later used. The Addressed As Slave (AAS) bit in status register is set when this address is received (the value in the data register is compared with the value in own address register). Note that the data and own address registers are offset by one bit; hence, programming the own address register with a value of 55h will result in the value AAh being recognized as the chip's SMBus slave address. After reset, own address register has default address 00h.
Table 65 - SMBus Own Address Register (SMBus Base Address +1)
OWN ADDR Default = 0x00 on VTR POR, VCC POR, PCI Reset or Soft Reset Bit Type D7 R/W Slave Address (bit 6) D6 R/W Slave Address (bit 5) D5 R/W Slave Address (bit 4) D4 R/W Slave Address (bit 3) D3 R/W Slave Address (bit 2) D2 R/W Slave Address (bit 1) D1 R/W Slave Address (bit 0) D0 R/W Command Bit Read = `1' Write = `0'
Bit Def
Data Shift Register The Data Register acts as serial shift register and read buffer interfacing to the SMBus. All read and write operations to/from the SMBus are done via this register. SMBus data is always shifted in or out of shift register. In receiver mode the SMBus data is shifted into the shift register until the acknowledge phase. Further reception of data is inhibited (SCLK pin held low) until the data shift register is read. In the transmitter mode data is transmitted to the SMBus as soon as it is written to the shift register if the serial I/O is enabled (ESO=1).
Table 66 - SMBus Data Register (SMBus Base Address +2) Default 0x00 on VTR POR, VCC POR, PCI Reset or Soft Reset DATA R/W D7 R/W D6 R/W D5 R/W D4 R/W D3 R/W D2 R/W D1 R/W D0 R/W
Note: Bytes are transferred most significant bit (MSB) first.
Clock Register
Overview
The Clock Register controls the internal SMBus clock generator, the SMBus reset, and the SCLK pin clock frequency (Table 67). The Clock register is 00H by default.
Table 67 - SMBus Clock Register (SMBus Base Address +3) D7 R/W SMB_RST (Note 1) D6 R D5 D4 D3 R R R RESERVED D2 R/W CLK_DIV D1 R/W CLK_SEL D0 R RESERVED DEFAULT 0x00 on VTR POR, VCC POR, PCI Reset or Soft Reset
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TYPE NAME
Note 1: The SMBus reset bit is not self-clearing.
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Bit 7 SMB_RST
The SMBus Reset bit D7 is used to reinitialize all the logic and registers in the SMBus block. SMB_RST is active high and is not self-clearing. To properly reset the the SMBus block, write the SMB_RST bit to `1' and then re-write the SMB_RST bit to `0'; i.e., the SMB_RST bit must be `0' for normal device operation. The SMB_RST bit is `0' by default.
Bit 6 - Bit 3
RESERVED
Bit 2 CLK_DIV
The CLK_DIV bit D2 is used to divide the SMBus input clock by two. When CLK_DIV = `0' (default) the SMBus input clock is not divided; when CLK_DIV = `1', the SMBus input clock, as well as the SMBus output clock SCLK, is divided by two.
Bit 1 CLK_SEL
The CLK_SEL bit D1 is used to enable the SMBus input clock. When CLK_SEL = `1', the SMBus inout clock is enabled and the SMBus block can operate normally; when CLK_SEL = `0' (default), the input clock is stopped and the SMBus will not run. The SMBus output clock SCLK frequency is determined by the CLK_SEL and CLK_DIV bits (Table 68).
Table 68 - SMBus Clock Select Encoding SMBUS CLOCK FREQUENCY CONTROLS CLK_SEL CLK_DIV 0 X 1 0 1 1 DESCRIPTION
CLOCK OFF SCLK = 100kHz SCLK = 50kHz
SMBus Timeouts
Overview
The SMBus is designed to provide a predictable communications link between a system and its devices. However some devices, such as a Smart Battery using a microcontroller to support both bus and maintain battery data, may require more time than might normally be expected. The following specifications take such devices into account while maintaining a relatively predictable communications. The following are general comments on the SMBus' timing: The bus may be at 0 kHz when idle. The FSMB Min is intended to dissuade components from taking too long to complete a transaction. An idle bus can be detected by observing that both the clock and data remain high for longer than THIGH Max. Every device must be able to recognize and react to a start condition at FSMB Max. See the Timing Diagrams Section for the SMBUS timing.
SMBus Timeout
The SMBus controller will indicate a timeout error when any clock low (SCLK) exceeds the TTIMEOUT value shown in SMBus timing table above. Timeout errors are identified using the TE bit in the SMBus Status register (see Status Register section).
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The SMBus master/slave controller does not implement hardware to release the clock/data lines upon detecting a timeout that exceeds the TTIMEOUT value shown in the Timing Diagrams Section for the SMBus timing. The SMBus master or slave can hold the SMBus indefinitely and the slave can respond improperly following a timeout, thereby restricting access to the SMBus by other devices on the bus. Software can issue a stop on the SMBus, or reset the master/slave controller by setting the SMB_RST bit. This can be done based on polling the TE bit or enabling interrupts based on SMBus timeout error.
Sample Transaction Diagram
The following figure illustrates a data transaction on the SMBus.
Send Address / Byte
SMB Clk
SMB Data
Start
0
1
0
1
1
0
1
0
Ack
FIGURE 7 - SAMPLE SMBUS SINGLE BYTE TRANSACTION
6.18 SMBus2 Slave Device
The LPC47S45x is equipped with two independent SMBus devices each with its own slave address that share the SCLK and SDAT pins. The first device, described in the previous section, is a master/slave controller and is referred to in this document as the SMBus. The second device, referred to as SMBus2, is a slave only device used to access internal SMBus2 Registers and the I/O devices on the X-Bus.
LPC47S45x
Master/ Slave (SMBus)
SCLK SDAT
SMBus device SMBus device
SMBus Host Controller
Slave (SMBus2)
FIGURE 8 - REPRESENTATIVE DIAGRAM OF SMBUS AND SMBUS2
The SMBus2 controller will maintain its slave address in the Runtime Register block at offset 0x76. The SMBus2 slave device has four possible bootable addresses by using the strapping options, SADR0 and SADR1, located on pins 101 and 103. Both the SMBus and SMBus2 have programmable slave addresses since they reside in read/write registers. In addition, since each of these devices have their own SMBus address, there is no need to provide any extra control signals between the two devices. Note: The SMBus2 controller is running at boot-up and may be accessed even if the processor fails. This allows the the system designer the ability to communicate with peripheral devices attached to the X-Bus from an external host controller. (i.e. the LCD controller, the Com 2 port, etc.). The SMBus and the LPC interface both access the X-Bus, therefore arbitration registers have been provided. The grant bit in these registers reflects the state of the logic that gives either bus control of the X-Bus. See section 6.18.3 X-Bus SMBus2/LPC Arbitration on page 137.
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6.18.1 SMBUS PROTOCOLS SUPPORTED BY SMBUS2
The SMBus2 supports two of the command protocols defined in the System Management Bus Specification, v1.1. Write Byte Read Byte After an SMBus transaction has been started, the first byte transmitted is always the Slave Address. Once a device acknowledges ownership of the slave address, the next byte transmitted by the host/master is the command code. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes are transferred with the most significant bit (MSB) first. The Read Byte and Write Byte protocols are shown.
Master to Slave Slave to Master S R/W A P = Start = Read/Write = Acknowledge = Stop Condition
S
Slave Address
Wr
A
Command Code
A
Data Byte
A
P
FIGURE 9 - WRITE BYTE PROTOCOL
S
Slave Address
Wr
A
Command Code
AS
Slave Address
Rd
A
Data Byte
AP
FIGURE 10 - READ BYTE PROTOCOL
Note 1: In the Read Byte Protocol there is no stop condition before the repeated start condition, and a "Not ACKnowledge" signifies the end of the read transfer.
6.18.2 COMMAND CODES
SMBus2 can access the SMBus2 Registers, nXCS0, XCS1, nXCS2, and nXCS3 through six predefined command codes listed in the following table. The four MSB of the command code are used to identify which X-Bus device should be accessed. The four LSB of the command code may be used as address or control bits and are mapped directly to XA[3:0] (i.e., bit[0]=XA[0], bit[1]=XA[1], etc.) LPC and SMBus2 arbitration registers control which interface is granted access to the X-Bus interface. Before the SMBus initiates an I/O cycle on the X-Bus, it should request access to the X-Bus in the SMB_ARB Arbitration Register located at offset 02h in the SMBus2 Registers. See 6.18.3 - X-Bus SMBus2/LPC Arbitration.
Note: When accessing the SMBus2 Registers, the four LSB are used as the address of the register that is to be read from or written to. When accessing an LCD controller on XCS1, the four LSB are used to determine the type (i.e., Data/Command) and direction (i.e., R/W) of the transaction. It is important that the type and direction embedded in the command code match the type and direction dictated by the SMBus protocol. Both of these SMBus transactions require the Write Byte and Read Byte protocols.
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Table 69 - Command Codes X-BUS DEVICE COMMAND CODE 0000 xxxx TYPE REGISTERS ACCESSIBLE
SMBus2 Registers LCDCS & CS1
R/W R/W
0001 xxxx
Registers 00h to 0B in SMBus2 Register Map are accessible by 4 LSB. Make CS1 active LCDS = RD + WR is used to latch the data. For LCD Controller operation, the 2 lowest bits must directly correspond to A0 and A1. (See Supported LCD Controllers on page 146) xx00 = Command Write xx01 = Command Read xx10 = Data Write xx11 = Data Read
Note: The least significant bit is R/W control bit. All reads are odd addresses and all writes are even addresses to X-Bus registers.
CS0
0010 xxxx
R/W
CS1
0011 xxxx
R/W
CS2
0100 xxxx
R/W
CS3
0101 xxxx
R/W
Set CS0 active. The 4 LSBs of the Command Code are forwarded to the X-Bus address pins (XA[3:0]). These bits can be used to address 8-bit external Registers (0h-Fh) or as control signals for devices connected on the X-Bus Set CS1 active. The 4 LSBs of the Command Code are forwarded to the X-Bus address pins (XA[3:0]). These bits can be used to address 8-bit external Registers (0h-Fh) or as control signals for devices connected on the X-Bus Set CS2 active. The 4 LSBs of the Command Code are forwarded to the X-Bus address pins (XA[3:0]). These bits can be used to address 8-bit external Registers (0h-Fh) or as control signals for devices connected on the X-Bus Set CS3 active. The 4 LSBs of the Command Code are forwarded to the X-Bus address pins (XA[3:0]). These bits can be used to address 8-bit external Registers (0h-Fh) or as control signals for devices connected on the X-Bus
Note: `x' denotes bits that can be set according to which registers need to be read or written. (i.e. if command code = 0000 0001 - Initiates Read/Write to SMB_DDR register, therefore the next Data Byte will be sent to that register, which will determine which of the specified peripheral will be enabled/disabled). If `xxxx' refers to an undefined register location the command is ignored. User Note: When a read/write is performed with an LCD controller, the direction (R/W) and type (Data/Command) must be part of the command code as shown in the table above. The direction of the transaction defined in the command code MUST match the direction defined by the SMBus protocol.
6.18.3 X-BUS SMBUS2/LPC ARBITRATION
The SMBus and the LPC interface can both access the X-Bus for I/O transactions. Therefore, two arbitration registers have been added to control access to the X-Bus interface. The LPC_ARB Arbitration Register has been added to the Runtime Register Block at offset 0x77 and the SMB_ARB Arbitration Register has been added to the SMBus2 Registers at offset 02h (see Table 71 on page 139).
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Both register have an X-Bus Access Request bit and an X-Bus Access Grant bit. Table 70 offers a summary of how each bus will be granted the X-Bus. Request Access to X-Bus When either bus wants to access the X-Bus, they must set Bit [0] of their respective arbitration register to `1'. Requests are granted on a first-come first-serve basis. Once a request is granted, no other request may be granted until the bus that is holding the X-Bus resets its request bit to `0'. Note: The request bit should remain high for the duration of the entire transaction. If removed prematurely and if the other bus is making a request, the transaction will be terminated and the new request will be granted. To ensure the SMBus can always gain control of the X-Bus, the SMB_ARB Arbitration register has a Master Request bit. If the LPC interface is unable to clear its request bit, the SMBus can assert a request by placing a `1' on bit[2] of the SMB_ARB Arbitration register. X-Bus Access Granted Each arbitration register has an X-Bus Access Grant bit, which is set by hardware only. Each bus must monitor their own grant bit to determine when they have been granted access to the X-Bus. Each interface should verify that access has been granted to them before initiating any I/O transactions. Note: The LPC Bus is granted access to the X-Bus by default at boot-up. The LPC interface should not clear the request bit until boot-up is complete.
Table 70 - SMBus2/LPC Arbitration Summary PAST STATE OUTPUTS SMB_GNT LPC_GNT 0 1 0 1 0 1 0 1 PRESENT STATE LPC_REQ 0 0 1 1 na 0 0 1 na INPUTS SMB_REQ 0 1 0 1 na 0 1 0 1 na SMB_MRQ 0 0 0 0 OUTPUTS SMB_GNT LPC_GNT 0 1 1 0 0 1 0 1
0 0 0 1 1 1 1 1
1 1 1 0 0 0 0 0
0 0 1 0 0 0 0 1
1 Note 1 1 0 1 0 1 1
0 Note 1 0 1 0 1 0 0
Note: The represents a transition from a `0' to a `1'. Note: na means not applicable (i.e. Don't Care). Note 1: If LPC_REQ and SMB_REQ "transition" to a `1' at the same time, arbitration logic produces either LPC_GNT='1' or SMB_GNT='1' based on a first-come first-serve basis. For the case when they transition to a `1' at the same time, circuitry is implented to prevent oscillation.
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6.18.4 SMBUS2 REGISTER SUMMARY
SMBus2 has a dedicated set of registers, accessible by the SMBus, that are used for disabling peripheral devices, arbitrating X-Bus access, and monitoring the length of time VCC and VTR are powered-on. These registers are listed in the following table. Notice that VCC_CNTx and VTR_CNTx are also accessible by the LPC interface through the runtime registers (See section 8 Runtime Registers on page 156).
Table 71 - SMBus2 Register Mapping Summary SMBUS2 REG OFFSET (HEX) 00 RUNTIME REGISTER OFFSET
NAME
TYPE
DESCRIPTION
SMB_Com2 SMB_DDR SMB_ARB Reserved Vcc_CNT1 Vcc_CNT2 Vcc_CNT3 Vcc_CNT4 Vtr_CNT1 Vtr_CNT2 Vtr_CNT3
R/W R/W R/W R/W R R R R R R R
Com Port 2 Enable/Disable SMBus2 Device Disable Control SMBus2/LPC Arbitration Reserved - Reads return zero. Vcc Power On Elapsed Time Counter, Byte 1 Vcc Power On Elapsed Time Counter, Byte 2 Vcc Power On Elapsed Time Counter, Byte 3 Vcc Power On Elapsed Time Counter, Byte 4 Vtr Power On Elapsed Time Counter, Byte 1 Vtr Power On Elapsed Time Counter, Byte 2 Vtr Power On Elapsed Time Counter, Byte 3
6Dh 6Eh 6Fh 70h 71h 72h 73h
01 02 03 04 05 06 07 08 09 0A
0B Vtr_CNT4 R Vtr Power On Elapsed Time Counter, Byte 4 74h Note: The VCC_CNTx registers and VTR_CNT registers are described in section 6.14 Power On Elapsed Timer (POET) on page 123 and in the Runtime Register section.
6.18.5 SMBUS2 REGISTER DESCRIPTION
Registers that are accessible by the LPC interface are described in the "Runtime Register" Section. All registers that are accessible by the SMBus only are described below. Com Port 2 Enable/Disable This register allows the user to tri-state the Com 2 port interface located on pins 93 and 95 to 101, giving the system designer the added flexability to mux an external COM Controller with this interface.
Table 72 - SMBus 2 SMB_COM2 Register Description NAME REG OFFSET (HEX) 00h TYPE DESCRIPTION
Bit [0] = Com 2 Disable 0 = Com 2 Interface Enabled Default = 0x00 1 = Com 2 Interface Disabled Bit [1] = Reserved on VCC POR and PCI Reset. Bit [2] = Reserved Bit [3] = Reserved Bit [4] = Reserved Bit [5] = Reserved Bit [6] = Reserved Bit [7] = Reserved Note: When the SMB_COM2, Bit [0] = 1, all COM Port 2 input pins are disconnected from the COM Port 2 controller. All output buffers on the COM Port 2 interface pins (i.e., pins 93, 95-101) are tri-stated, regardless of whether they are configured for GPIO or UART functionality. The Com Port 2 input pins are held in an inactive state as described in Table 73.
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Table 73 - COM Port 2 Inactive Signal State COM PORT 2 SIGNAL RI2# I/O INACTIVE STATE
I I I O I O I O
H H L na H na H na
DCD2# RXD2 TXD2 DSR2# RTS2# CTS2# DTR2# SMBus2 Device Disable Control
This register enables/disables the Floppy Port, Serial Ports 1 and 2, and the Parallel Port. The SMBus2 DDR Register is identical in operation to the LPC Device Disable Register in the Runtime Registers Block, at offset 22h, except for interaction with signal DDRC (pin 31). If a device is disabled in either register it will be disabled to both interfaces. To set a device to be enabled, both registers must set the respective enable bit to `0'. Bit [1], Register Lock, of the SMBus2 DDR register only affects R/W status of the SMBus2 DDR register.
Table 74 - SMBus 2 SMB_DDR Register description SMBus2 REG OFFSET (hex) SMBus2 Device 01 Disable Register, SMB_DDR READ/WRITE when Default = 0x00 Device Disable on VCC POR and Register Bit[1] = 0 PCI Reset. NAME DESCRIPTION
Bit[0] Floppy Write Protect. 0= no effect: floppy write protection is controlled by the write protect pin or the Forced Write Protect bit (bit 0 of register 0xF1 in Logical Device 0); 1= Write Protected. If set to 1, this bit overrides the write protect pin on the part and the forced write protect bit. nWRTPRT (to the FDC Core) = WP (FDC SRA Register, Bit 1) = (Floppy Write Protect) OR nWRTPRT(from the FDD Interface) OR (nDS0 AND Force Write Protect ) OR (nDS1 AND Force Write Protect ). Note: The Force Write Protect bit is in the FDD Option Configuration register. Bit[1] Register Lock This bit is cleared on VCC POR and PCI Reset. 0 - No effect (Default) 1 - All of the bits in this register are Read Only until a VCC POR or PCI RESET. Bits[2] Reserved. Return 0 on read. Bit[3]: Floppy Enable. 0=No effect: FDC controlled by its activate bit; 1=Floppy Disabled Bit[4] Reserved
READ-ONLY when Device Disable Register Bit[1] = 1
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NAME
SMBus2 REG OFFSET (hex)
DESCRIPTION
Bit[5] Serial Port 2 Enable 0=No effect: UART2 controlled by its activate bit; 1=UART2 Disabled Bit[6] Serial Port 1 Enable. 0=No effect: UART1 controlled by its activate bit; 1=UART1 Disabled Bit[7] Parallel Port Enable. 0=No effect: PP controlled by its activate bit; 1=PP Disabled Note: If "0" (enabled), bits[7:3] have no effect on the devices; devices are controlled by their respective activate bits. If "1" (disabled), bits[7:3] override the activate bits in the configuration registers for each logical block. Note: Any peripheral that is disabled in this register will not be accessible by either the LPC interface or the SMBus. See the LPC Device Disable Register in the Runtime Register section. SMBus2, SMB_ARB Arbitration Register This register is used to request access to the X-Bus through Bit[0]. If the request is granted, Bit[1] will be set to `1' by the hardware. The host/master should monitor this bit to know when to initiate an I/O cycle. If the the LPC interface locks up or cannot remove its request, an SMBus master request is available on Bit[3]. If this bit is asserted, any active LPC transactions are immediately terminated.
Table 75 - SMBus2, SMB_ARB Arbitration Register NAME SMBus2 REG OFFSET (hex) 02 DESCRIPTION
SMB_ARB Arbitration Register
Bit 0 and Bit 2 are R/W by the Default = 0x00 on VCC POR and SMBus2, Bit 1 is set/reset PCI Reset. by the arbitration logic, and Read only by the SMBus2. Note: Since both the LPC Bus and SMBus are able to access the X-Bus, arbitration registers have been provided. It is important to note that when XMB_MREQ=1, accesses to the X-Bus by the SMBus will take precedence over accesses made by the LPC Bus. That means any transaction initiated by the LPC bus will be immediately terminated.
Bit [0] = SMB_REQ, SMBus2 X-Bus Access Request Bit [1] = SMB_GNT, SMBus2 X-Bus Access Grant Bit [2] = SMB_MREQ SMBus2 X-Bus Master Request Bit [3] = Reserved Bit [4] = Reserved Bit [5] = Reserved Bit [6] = Reserved Bit [7] = Reserved
6.18.6 INVALID COMMAND PROTOCOL RESPONSE BEHAVIOR
The LPC47S45x registers that are accessed with an invalid command protocol will not be updated. A register will only be updated following a valid command protocol. The only valid commands are the read byte and write byte commands described in section 6.18.1 SMBus Protocols supported by SMBus2. Invalid Slave Address If the host sends an invalid slave address, the SMBus2 interface will not respond and it will return to its idle state Invalid Register Address
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If the SMBus Slave Interface receives an invalid Register Address after acknowledging a valid slave address and a write field bit, it will follow through with the command protocol (if the command protocol from the master is correct). It will latch the register address and ACK. In the case of a read byte command, it will ACK the second START, slave address and read field, but return zero data. In the case of a write byte command, it will ACK the register data but it will have no effect. If the command protocol from the master is not correct, it will respond as described below. Slave Receives Multiple Byte Read Command Protocol This condition pertains to an attempt by the host to transfer two or more bytes in a read command. If the SMBus Slave Interface receives an ACK after the first register data byte it will stop responding and return to idle. Note: This pertains to an attempted autoincrement read as in I2C. The LPC47S45x does not support the SMBus block read command. Slave Receives Multiple Byte Write Command Protocol This condition pertains to an attempt by the host to transfer two or more bytes in a write command. If the SMBus Slave Interface receives a second data byte following the register data byte ACK, it will stop responding (NACK) and return to the idle state. Note: This pertains to an attempted autoincrement write as in I2C. The LPC47S45x does not support the SMBus block write command and if a byte count is given in the data byte field, it will be interpreted as data. Improper Field Within Command Protocol If the SMBus slave interface receives an improper field, it will stop responding and return to the idle state. Several cases follow. Note that by not responding, a NACK will be produced in the ACK/NACK field that follows the improper field.
Stop Flag Received During Command/Data Expectation
If the SMBus Slave Interface receives a STOP where it is not expected, it will not respond and return to idle.
Start Sequence Received in Middle of Transaction
If the SMBus Slave Interface receives a correct start sequence (start bit, valid slave address and write bit) in the middle of a transaction (not a read byte transaction) it will stop responding and return to idle.
Read Field Received Following the First Slave Address
If the SMBus Slave Interface receives a read bit following the first slave address (excluding the bit field following the second slave address of a read command), it will not respond and then return to idle.
Write Field Received Following the Second Slave Address of a Read Command
If the SMBus Slave Interface receives a write bit following the second slave address of a read command, it will not respond and then return to idle.
6.18.7 SLAVE DEVICE TIME-OUT
The SMBus2 slave device will always time-out when SCLK is held low longer than TTIME-OUT Max = 35ms. The SMBus Slave Interface resets and returns to idle if SCLK is held low for longer than TTIME-OUT Max.
6.18.8 STRETCHING THE SCLK SIGNAL
The LPC47S45x supports stretching of the SCLK low time between byte transfers (byte+ACK). The SMBus2 slave device will not hold the SCLK low longer than ten CLOCKI pulses.
6.18.9 SMBUS TIMING
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See FIGURE 37 in the Timing Diagrams section.
6.18.10 BUS RESET SEQUENCE
The SMBus Slave Interface will reset and return to the idle state upon a START field followed immediately by a STOP field.
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6.19 X-Bus Interface
The X-Bus interface is capable of performing I/O cycles initiated by either the SMBus or the LPC interface. This interface allows the LPC47S45x to interface to as many as 4 external components that have an 8 bit data bus and occupy up to 4 contiguous I/O address ports. The LPC47S45x decodes I/O cycles received from the LPC interface and if the transaction is valid the X-Bus will activate the appropriate chip select.
Note: Before initiating an I/O cycle, the SMBus or the LPC interface should verify that it has been granted access to the X-Bus. Note: External pullups are required on the nXRD and nXWR pins. Note: The X-Bus interface is powered by VCC only.
6.19.1 I/O CYCLES
I/O cycles may be initiated on the X-Bus by either the SMBus or LPC interfaces. Since both interfaces can request the X-Bus, a simple arbitration scheme has been implemented on a "first-come, first-serve" basis, where the request not chosen is simply ignored. All I/O transactions will be decoded, but only the bus that wins arbitration will be given access to the X-Bus interface. See section 6.18.3 X-Bus SMBus2/LPC Arbitration on page 137 for a more detailed description of arbitrating access to the X-Bus. The X-bus chip selects XCS1, nXCS2, and nXCS3 have an associated disable bit. This bit allows each chip select to be individually enabled or disabled. This bit is part of the X-bus Low Address Byte Configuration register. The X-bus chip selects, XCS1, nXCS2, and nXCS3, base address register has an associated "write protect" bit that can only be set once, and is reset by VCC POR and PCI Reset. When this bit is set, it prevents the base address configuration registers (high byte and low byte) for each chip select from being written. This security feature ensures that the base address and disable bit for each chip select can only be set by BIOS and cannot be corrupted by any virus software. This bit is part of the X-bus Low Address Byte Configuration register. Note: nXCS0 does not have the disable bit or the write protect bit so that it may be used to support snooping on port 80h. Note: All the chip selects are active low except XCS1. This chip select was designed to support an LCD controller, which needs an active high signal. See section 6.19.2 Supported LCD Controllers. The read and write strobes have address setup and hold times, and pulse widths, that are compatible with X-Bus timing of the Intel PIIX4. See the timing diagrams in the "Timing" section. The strobes will only become active during an LPC cycle in which the LPC address matches the corresponding X-bus address or during an SMBus initiated cycle in which the SMBus Command Code matches the corresponding chip select command code. When the read/write strobes become active, the bus that wins arbitration will either read/write the data presented on the XD[7:0] pins. SMBus Initiated I/O Cycles The X-Bus interface may be accessed by the SMBus2 controller for I/O transactions. (See section 6.18 SMBus2 Slave Device) The X-Bus interface will decode the four MSB (i.e., bits[7:4]) of the command code received on the SMBus. If the command code received matches one of the command codes defined in Table 69 then the appropriate chip select will be made active. The four LSB (i.e., [3:0]) of the command code will be forwarded to address bits XA3 to XA0 respectively. LPC Initiated I/O Cycles The X-Bus interface may be accessed by the LPC interface for I/O transactions only. See section 6.3 LPC Interface on page 24 for supported LPC I/O cycles. The chip select outputs are generated by circuitry in the LPC47S45x that compares the LPC I/O address bits with the X-bus base I/O address configuration registers.
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Chip Selects The LPC47S45x performs 16-bit address qualification on the X-Bus base I/O addresses. That is, the upper 4-bits, bits[15:12], must be `0'. Note: Bit 6 of the OSC Global Configuration Register (CR24) must be set to `1' for 16-bit address qualification.
Note: The four LSB of the Address (or Command Code) are always forwarded to the address signals XA[3:0], regardless of what mode is programmed in the X-Bus Selection Configuration Register. nXCS0
Chip select zero is activated only if the I/O address bits 12 to 15 are zero and bits 0 to 11 match the Base I/O Address, which is stored in Logical device 8 at offsets 60h and 61h.
XCS1
Chip select one is activated only if the I/O address bits 12 to 15 are zero and bits 2 to 11 match the Base I/O Address, which is stored in Logical device 8 at offsets 62h and 63h.
nXCS2 and nXCS3
Activation of chip selects two and three are dependent on the Mode of Operation selected. See below. Modes of Operation This interface has been designed to operate in two modes of operation. Both modes offer 4 separte chip selects (nXCS0 - nXCS3), a read strobe (nXRD), a write strobe (nXWR) and an 8 bit data bus (XD0 - XD7). External pullups are required on the nXRD and nXWR pins. The mode of operation determines the number of bits in the base I/O addresses required to activate nXCS2 and nXCS3. The mode is chosen via bit 0 of the X-Bus Selection Configuration Register located in Logical Device 8 at 0xF0. In X-Bus Mode 1, the X-bus base I/O address configuration registers for nXCS2 and nXCS3 contain address bits A15 through A8 and A7 through A2, respectively. A1 and A0 pass directly through to XA1 and XA0, respectively. The chip selects only become active for the LPC bus cycle in which the address match occurs. In X-Bus Mode 2, the X-bus base I/O address configuration registers for nXCS2 and nXCS3 contain address bits A15 through A8 and A7 through A4, respectively. A3, A2, A1 and A0 pass directly through to XA3, XA2, XA1 and XA0, respectively. The chip selects only become active for the LPC bus cycle in which the address match occurs. See FIGURE 11 for a representative diagram of the operation of the X-Bus interface in both Modes 1 and 2. Notice that nXCS0 and XCS1 operate the same in Modes one and two. X-Bus Chip Select Base I/O Address Registers The Base I/O Address Registers for the X-bus are defined in the Configuration section. See Table 93 - X-Bus, Logical Device 8 [Logical Device Number = 0x08] on page 214. X-Bus I/O Configuration Register X-Bus Selection Register is used to select the X-bus mode and the pulse widths of the X-bus read and write strobes. This register is located in Logical Device 8 at an offset of 0xF0. See the Configuration section for register description. See the "Timing Diagrams" section for figures that show "representative" LPC I/O to X-bus cycle timing.
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The following figure shows the X-bus Interface (Shaded areas operate differently in Mode 1 and Mode 2).
SMBus2 Command Code LPC Address LPC Data/ SMBus2 Data LPC/SMBus2 R/W Command
8
12
I/O ReadnXRD Active
I/O WritenXWR Active 8-bit Data Bus
X-Bus CS0 Base Address Configuration Register
12-bit Address Comparator 4-bit Command Code Comparator (0010)
a LPC/ SMBus2 Mux
nXCS0
X-Bus CS1 Base Address Configuration Register Disable
10-bit Address Comparator 4-bit Command Code Comparator (0011) 4-bit (LCD) Command Code Comparator (0001) 10-bit (Mode 1) / 10/8-bit Address 8-bit(Mode 2) Comparator Address Comparator 4-bit 4-bit Command Code Command Code Comparator Comparator (0100) (0100) 10/8-bit Address 10-bit (Mode 1) / Comparator 8-bit(Mode 2) Address Comparator 4-bit Command Code 4-bit Comparator Command Code (0101) Comparator (0101) a a 4 4 4 4 LPC/SMBus2 LPC/SMBus2 Mux Mux
a LPC/ SMBus2 Mux
XCS1
nXRD nXWR
LCDS a a LPC/ LPC/ SMBus2 SMBus2 Mux Mux a a LPC/ SMBus2 LPC/ Mux SMBus2 Mux nXCS2 nXCS2
X-Bus CS2 Base X-Bus CS2 Base Address Configuration Address Configuration Register Disable Register Disable
X-Bus CS3 Base Address Configuration X-Bus CS3 Base Register Disable Address Configuration Register Disable
nXCS3 nXCS3
XAA0 XAA0 XAA1 XAA1 XAA2 XAA2 XAA3 XAA3
a
- Arbitration Logic for LPC and SMBus2 access for X-Bus
FIGURE 11 - LPC AND SMBUS I/O ACCESSES TO THE X-BUS INTERFACE (MODE 1/MODE 2)
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6.19.2 SUPPORTED LCD CONTROLLERS
The following table lists LCD controllers supported by the LPC47S45x and their corresponding signals. Chip select 1, XCS1, is active high to support these LCD controllers without any external logic.
Table 76 - LCD Controller Connections LPC47S45X SIGNAL HITACHI HD61202U SIGNAL CS3 MOTOROLA MC141803 SIGNAL CE
XCS1 LCDCS A0 A1 XD0-XD7
E RW D/I DB0-DB7
CS# R/W# D/C# DO-D7
The two least significat address bits are used to communicate the type and direction of a transaction initiated with the LCD controller. A1 determines if the transaction is a command or data type and A0 determines is the transaction is a read/write.
Table 77 - LCD Controller Operations A1 A0 LCD CONTROLLER OPERATION Command Write
0 0 1 1
0 1 0 1
Command Read Data Write Data Read
Note: The direction of LCD Controller Operation (i.e. Read/Write) must match the direction of the command issued by either the LPC interface or the SMBus.
Timing for SMBus initiated cycles accessing the LCD controller are shown in the Timing Diagrams section.
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7
ACPI/PME/SMI FEATURES
The LPC47S45x supports ACPI as described in this section. Note on Terminology in this Document: A wake event results in the nPS_ON pin going active low. A PME event results in the nIO_PME pin going active low. The LPC47S45x supports legacy SMI events, power management events (PME) and the ACPI register set for SCI event handling. The following sections will give an overview of the power supply states supported on the LPC47S45x, the ACPI registers and features offered, and a description of PME and SMI event handling.
Note: The PM1 and GPE registers located in the Runtime Register block are ACPI specific registers used to support SCI event handling. In addition, there is a Power Supply register in the Configuration Register block, Logical Device A at offset 0xF8, that is used to control/enable the power supply states, sleep control, and the SMI/SCI select capability for legacy support.
7.1
Power States
The ACPI Specification defines Global Sytem State Definitions, Device Power State Definitions, and Sleep State definitions. The following sections show the power states that are supported in hardware by the LPC47S45x.
7.1.1
GLOBAL/SYSTEM SLEEP STATES
There are four Global System states and five System States as defined by the "Advanced Configuration and Power Specification," Rev 1.0b. Listed below are the supported Global and System states.
1. G3 - Mechanical Off (VCC=0V, VTR=0V) This state is entered when power is totally removed from the system (i.e., pulling the plug). This is the only safe state to operate on the hardware without damaging it. Except for the Real Time Clock, power consumption is zero. See Table below for power supply states for "Mechanical Off". G2/S5 - Soft Off(VCC=0V, VTR=3.3V) This state is entered when software writes a `1' to the SLP_EN bit while the SLP_TYPx bits [4:2]=111. The system can be awakened by the power button or a wake-up event (i.e., wake on specified key, RTC alarm, etc.). This state is also entered when a power button over-ride event occurs, which is generated when a user presses the power button for more than four seconds while the system is in the working state. If a power button over-ride event is used to put the system into a Soft Off state, then the Power Button must be used to wake the system from this state. The system will not respond to wake-up events. See section 7.3.2 Power Button With Override on page 150. G1/S4 - Sleeping(VCC=0V, VTR=3.3V) This state is entered when software writes a `1' to the SLP_EN bit while the SLP_TYPx bits [4:2]=110. The system can be awakened by the power button or a wake-up event (i.e., wake on specified key, RTC alarm, etc.). G0/S0 - Working (VCC=3.3V, VTR=3.3V)
2.
3.
4.
All functional blocks are fully powered and operational in this state. 7.1.2 DEVICE SLEEP STATES
Each device in the LPC47S45x supports two device sleep states, D0 (on) and D3 (off). The D3 state corresponds to the PCI defined D3 cold state. With all devices off, the part is powered either by main power (VCC) or by standby power (VTR), depending on the system Sleep State. In both cases, the part can provide wakeup capability through the power management logic and generate an IO_PME# or IO_SMI#. In an ACPI system, the devices are powered on and off through control methods.
7.1.3
WAKE EVENTS
Wake events are events that turn power on (i.e. activate nPS_ON) if enabled. These events can be also enabled as SMI, PME, or SCI events as shown in the following table. It should be noted that all enabled SCI events in the PM1 and GPE1 registers will directly generate a signal into the wakeup logic to turn on the power supply when VCC=0V, except if a power button override was used to turn VCC off.
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If a power button override was used to remove VCC, then only the power button can be used to return VCC power to the system. See FIGURE 12 "Wakeup Logic" on page 149.
Table 78 - SMI/PME Generation WAKE EVENTS INPUT TO WAKE-UP LOGIC (PM1/GPE REGISTERS ONLY) (Note 1) nRI1_STS or ALL_PME_STS (Note 2) SMI/PME GENERATION SMI/PME
Active transitions on the ring indicator inputs nRI1 Active transitions on the ring indicator inputs nRI2 Active keyboard-data edges on KDAT Active mouse-data edges on MDAT Wakeup on Specific key Programmable edges on GPIO pins
GP50/RI2 or ALL_PME_STS (Note 2) KDAT_STS or ALL_PME_STS (Note 2) MDAT_STS or ALL_PME_STS (Note 2) SPEKEY_STS or ALL_PME_STS (Note 2) GP23_STS, and GP[50:57]_STS or ALL_PME_STS (Note 2) GP34_STS & GP35_STS ALL_PME_STS (Note 2) RTC_STS PWRBTN_STS VTR_POR_STS
SMI/PME SMI/PME SMI/PME SMI/PME SMI/PME PME (Note 3) SMI/PME PME (Note 3) PME (Note 3)
Fan tachometer event RTC alarm event Power Button on (nPB_IN asserted low) VTR POR if VTR_POR_EN bit is set
- VTR POR if the nPS_ON pin was active VTR_POR_STS - low prior to the loss of VTR and neither the VTR_POR_OFF bit nor the VTR_POR_EN bit is set Note: Any PM1/GPE event can generate a PME or SMI and can initiate the wake-up logic on the chip. Note 1: When the PWRBTNOR_STS bit is set only the power button can wake the system. All other inputs into the wake-up logic are blocked by this bit. Note 2: The ALL_PME_STS bit will only be set if the PME event is enabled in the PME enable registers (PME_ENx) located in the Runtime Register block. Note 3: These PME events are enabled in the PM1 and GPE registers only.
The following are SMI events that are not wake events: Floppy Interrupt Parallel Port Interrupt WDT P12 UART1 and UART2 interrupts Mouse and keyboard interrupts SLP_EN Any wakeup logic that affects the configuration of the wakeup events is implemented so that the configuration of the wakeup events is retained (in the event of total power loss) upon Vtr POR.
7.2
ACPI specific Registers
The ACPI specification has defined specific registers for SCI event handling. The LPC47S45x has implemented the Power Management registers and the General Purpose Event Registers (PM1 and GPE status and enable registers) in the Runtime Register block to handle SCI events. An SCI event, if enabled, will generate an IO_PME# and initiate the wake-up logic. These registers do not interfere with or effect the PME registers located in the Runtime Register block. According to the ACPI specification, a legacy switch has been incorporated to control if an SMI or an SCI is generated. See section 7.3.1 Legacy/ACPI Select on page 150. The following diagram illustrates the ACPI specific registers and the PME registers.
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Note: SCI events are those illustrated in the diagram as the PM1 and GPE1 registers.
ALL 42x PME Events
. . . + nRI1 PME_STSx, PME_ENx Registers KDAT MDAT SPEKEY GP23 GP34 GP35
GPE1_STS2Reg GPE1_EN2Reg PME_STS GPE1_STS1Reg GPE1_EN1Reg IO_PME#
ALL_PME
PME_EN
+
SCI_EN SMI#
GP50/nRI2 . . . GP57
SMI_SCI_ENB
. . .
. . .
SLP_CTRL SLP_EN Note: SLP_CTRL=1 disables sleep when the SLP_EN bit is written to `1'. Note: the PWRBTN is always enabled for wakeup
PM1_STS2Reg
PM11_EN2Reg
PWRBTN RTC
These events are blocked from waking the Other Wakeup Events: system if the PWRBTNOR_STS bit is set. *AL_REM_EN *VTR_POR if VTR_POR_EN bit is set *VTR POR if the nPS_ON pin was active low prior to the loss of VTR and neither the VTR_POR_OFF bit nor the VTR_POR_EN bit is set
To Wakeup Logic (Power Supply Control)
FIGURE 12 - WAKEUP LOGIC
Notice in the diagram above that any event enabled in the PM1 or GPE registers will always generate a signal to initiate the wakeup logic to the power supply (i.e. activate nPS_ON). In addition, the SCI registers are able to generate a PME or an SMI if enabled. The following is a list of options for generating PMEs and SMIs.
1. PME status and enable registers. (asserts IO_PME# only) To generate a PME, enable individual PME events in the PME_ENx registers and enable the PME_EN register. The PME_EN register enables the chip to assert the IO_PME# signal. SMI status and enable registers. (asserts IO_SMI# only) To generate an SMI, enable individual SMI events in the SMI_ENx registers and enable Bit[7] EN_SMI in the SMI_EN2 register at offset 17h. The EN_SMI bit enables the chip to assert the IO_SMI# signal. Note: SMI can be routed to the Serial IRQ by setting Bit[6] of the SMI_EN2 register. PM1 and GPE status and enable registers (ACPI Specific Registers) (SCI event = Assert IO_PME# and wake the system) To generate an SCI event, enable individual events in the PM1 and GPE registers and enable the SCI_EN bit in the PM1_CNTRL1 register at offset 60h in the Runtime Register block. The SCI_EN bit enables these events to assert the IO_PME# signal. Note: If the ALL_PME_EN bit is set, then all enabled PME events will generate an IO_PME# and wake the system regardless of the PME_EN register. -
2.
3.
(assert IO_SMI# and wake the system) To generate an SMI event through the SCI registers, enable individual events in the PM1 and GPE registers, set the SCI_EN bit to `0', set the SMI_SCI_ENB bit to `0' found in the PS_CNTRL register, and set the EN_SMI bit to `1' in the SMI_EN2 registers at offset 17h.
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7.3
7.3.1
ACPI Features
LEGACY/ACPI SELECT
These features comply with the ACPI Specification, Revision 1.0b.
The LPC47S45x supports both legacy operating systems and ACPI systems. System software for legacy power management consists of an SMI interrupt handler while for ACPI it consists of the ACPI driver (SCI interrupt handler). Therefore, the LPC47S45x offers both SMI specific registers (i.e., SMI_ENx & SMI_STSx) and it offers ACPI specific registers, referred to as PM1 and GPE1 registers. If SCI generation is enabled then all power management events enabled in the PM1 and GPE registers will generate an IO_PME# and initiate the wake-up logic on the chip. It is also possible to enable the SCI registers to generate an SMI signal.
Note: Any enable event in the PM1 and GPE1 registers will always generate a signal into the wake-up logic.
Therefore, the following options have been made available for both legacy and ACPI systems. See section 7.2 ACPI Specific Registers on page 148 for a description of how to implement the ACPI specific registers. The LPC47S45x offers three options for the SMI/SCI select capability:
1. 2. 3. SMI only Enable SMI registers to generate an IO_SMI# events only. SMI with wakeup Enable PM1 and GPE registers to generate an IO_SMI# and a wakeup event SCI Select Enable PM1 and GPE registers to generate an IO_PME# and initiate wake-up (i.e., IO_SMI# signal not generated). SCI events are also referred to as PME events
Note: Only events enabled in the PM1 or GPE registers can set a status bit to initiate a signal directly into the wakeup logic on the LPC47S45x. Events enabled in the SMI registers can only generate an IO_SMI# signal, they can never generate a signal to initiate wakeup directly. Note: The PME events generated by the PM1 and GPE1 registers have no effect on the PME events in the PME_EN and PME_STS registers. Note: Wake-up events in the PM1 and GPE registers cannot initiate a wakeup event after a power button override has occurred.
7.3.2
POWER BUTTON WITH OVERRIDE
The power button switches the system from the sleeping/soft off state to the working state, and signals the OS to transition to a soft off state from the working state. The power button has status and enable bits in the PM1 status and enable registers. When the power button is pressed for less than four seconds it will always set the PWRBTN_STS bit on the button press (high-to-low) edge. If nPS_ON is inactive, it will generate a signal into the wakeup logic to assert the nPS_ON signal active low. (Note: When nPS_ON is pulled low, the power supply is turned on and VCC goes to 3.3V.) If the PWRBTN_EN bit is set, a PME, SCI or SMI may also be generated depending on the state of the PME_EN bit in the PME Enable register, the SCI_EN bit in the PM1_CNTRL1 register and the SMI_SCI_ENB bit in the PS_CNTRL register. If the power button is held for more than four seconds when VCC is active, a power button override will be initiated and VCC will be shut off. Once a power button override occurs, only a power button press (an active nPB_IN signal) can wake the system. The power button override event, as required by the ACPI specification, will transition the system to the soft-off state. The PM1 status register has a bit, called PWRBTNOR_STS that gets set to indicate an override event has occurred. This event clears the PWRBTN_STS bit. This override event is described as follows: If the user presses the power button for more than 4 seconds while the system is in the working state, a hardware event is generated and the system will transition to the soft off state.
Note: The power buttonalways results in a wake-up event (if nPS_ON is inactive), regardless of the setting of PWRBTN_EN. Note: The LPC47S45x may also be powered down by software writing a `1' to the PSOFF bit located in the Power Supply Control Register (PS_CNTRL).
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7.3.3
RTC ALARM AS A PME EVENT
The ACPI specification requires that the RTC alarm generate a hardware wake-up event from the sleeping state. For a description of the RTC alarm, see section 6.9 Real Time Clock - General Description on page 97. The RTC alarm may be enabled by the RTC_EN bit in the PM1 Enable Register. If enabled, an RTC alarm event will generate a signal into the wake-up logic to activate the nPS_ON signal and will set the RTC_STS bit in the PM1_STS register. If the SCI_EN bit is set, the enabled RTC alarm will generate a PME event. Note: If the SCI_EN bit is not set and the SMI_SCI_ENB bit is set to `0' and the EN_SMI bit is set to `1' in the SMI_EN2 register, then an SMI will be generated for the enabled RTC event. Note: The RTC Alarm is not an option in the PME registers, it can only generate a PME event if enabled in the Power Management 1 Enable Register 2 (PM1_EN2). It does NOT require that the PME Enable bit in the PME_EN register be set in order to generate an nIO_PME. The RTC Alarm is equipped with an Alarm Remember Enable bit (AL_REM_EN) in the PS_CNTRL registers, Logical Device A at 0xF8. If the alarm is set to wake the system during a period of time in which VTR=0 and the AL_REM_EN bit is set, then when VTR power is restored to the system the alarm will be activated and thereby wake the system.
7.4
PME Support
The LPC47S45x offers support for power management events (PMEs). PME events can be generated from the PME, status and enable, registers or by the PM1 and GPE registers implemented to support System Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the IO_PME# signal. In the LPC47S45x, the IO_PME# is asserted by: Active transitions on the ring indicator inputs nRI1 and nRI2 Active keyboard-data edges Active mouse-data edges Wakeup on Specific key Super I/O Device Interrupts Watchdog Timer Programmable edges on GPIO pins Fan tachometer event RTC alarm event Power Button event The GP42/nIO_PME pin, when selected for the nIO_PME function, can be programmed to be active high or active low via the polarity bit in the GP42 register. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP42 register. The nIO_PME pin function defaults to active low, open-drain output. PME functionality is controlled by the PME status and enable registers in the runtime registers block, which is located at the address programmed in configuration registers 0x60 and 0x61 in Logical Device A. The PME Enable bit, PME_EN, globally controls PME Wake-up events. When PME_EN is inactive, the IO_PME# signal can not be asserted by events in the PME_STS registers. When PME_EN is asserted, any wake source whose individual PME Wake Enable register bit is asserted can cause IO_PME# to become asserted. The PME Status register indicates that an enabled wake source has occurred and if the PME_EN bit is set, asserts the IO_PME# signal. The PME Status bit is asserted by active transitions of PME wake sources. PME_STS will become asserted independent of the state of the global PME enable, PME_EN. The following pertains to the PME status bits for each event: The output of the status bit for each event is combined with the corresponding enable bit to set the PME status bit. The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status bit are cleared on a write of `1'. For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the polarity bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high
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edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding PME status bits. Status bits are cleared on a write of `1'. The PME Wake registers also include status and enable bits for the fan tachometer input. See the "Keyboard and Mouse PME Generation" section for information about using the keyboard and mouse signals to generate a PME. The P12 and P16 bits enable a PME event on single high-to-low edge or on both high-to-low and low-to-high edges. Default is single edge. There is also a polarity select bit in the configuration register at 0xF0 in logical device 7. The register that selects the edge, Edge Select register, is located at the address programmed in the Base I/O Address register in the Logical Device A at an offset of 21h. Refer also to PME Status and Enable register 9. See the Runtime Registers sections for description on these registers. If both edges are selected for generating a PME via P12 and P16, then the PME is generated on each edge until the corresponding PME status bit is cleared. Note that P12 and P16 status bits are cleared on by write of `1'. The SMI generated by P12 and P16 is deasserted when the associated PME status bit is cleared. In the LPC47S45x the IO_PME# pin can be programmed to be an open drain, active low, driver. The LPC47S45x IO_PME# pin is fully isolated from other external devices that might pull the IO_PME# signal low; i.e., the IO_PME# signal is capable of being driven high externally by another active device or pull-up even when the LPC47S45x Vcc is grounded, providing VTR power is active. The LPC47S45x IO_PME# driver sinks 6mA at .55V max (see section 4.2.1.1 DC Specifications, page 122, in the PCI Local Bus Specification, Revision 2.1). The PME registers are run-time registers as follows. These registers are located in system I/O space at an offset from Runtime Registers Block, the address programmed in Logical Device A at registers 0x60 and 0x61. The following registers are for GPIO wakeup events: PME Wake Status 2 (PME_STS2), PME Wake Enable 2 (PME_EN2) PME Wake Status 3 (PME_STS3), PME Wake Enable 3 (PME_EN3) PME Wake Status 4 (PME_STS4), PME Wake Enable 4 (PME_EN4) PME Wake Status 5 (PME_STS5), PME Wake Enable 5 (PME_EN5) PME Wake Status 7 (PME_STS7), PME Wake Enable 7 (PME_EN7) The PME Wake Status 6 (PME_STS6), PME Wake Enable 6 (PME_EN6) registers are for the device interrupt PME events. The PME Wake Status 1 (PME_STS1), PME Wake Enable 1 (PME_EN1) registers are for pin and internal function PME events. See PME register description in the Runtime Register Section.
7.4.1
`WAKE ON SPECIFIC KEY' OPTION
The LPC47S45x has logic to detect a single keyboard scan code for wakeup (PME generation). The scan code is programmed onto the Keyboard Scan Code Register, a runtime register at offset 0x5F from the base address located in the primary base I/O address in Logical Device A. This register is powered by VTR and reset on VTR POR. The PME status bit for this event is located in the PME_STS1 register at bit 5 and the PME enable bit for this event is located in the PME_EN1 register at bit 5. See the Runtime Register section for a definition of these registers. Data transmissions from the keyboard consist of an 11-bit serial data stream. A logic 1 is sent at an active high level. The following table shows the functions of the bits.
BIT FUNCTION Start bit (always 0) Data bit 0 (least significant bit) Data bit 1 Data bit 2 Data bit 3
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BIT
6 7 8 9 10 11
FUNCTION Data bit 4 Data bit 5 Data bit 6 Data bit 7 (most significant bit) Parity bit (odd parity) Stop Bit (always 1)
The timing for the keyboard clock and data signals are shown in the "Timing Diagrams" section. The process to find a match for the scan code stored in the Keyboard Scan Code register is as follows: Begin sampling the data at the first falling edge of the keyboard clock following a period where the clock line has been high for 115-145usec. The data at this first clock edge is the start bit. The first data bit follows the start bit (clock 2). Sample the data on each falling edge of the clock. Store the eight bits following the stop bit to compare with the scan code stored in the Keyboard Scan Code register. Sample the comparator within 100usec of the falling edge of clock 9 (for example, at clock 10). Sample the parity bit and check that the 8 data bits plus the parity bit always have an odd number of 1's (odd parity). The process repeats until a match is found. If the 8 data bits match the scan code stored in the Keyboard Scan Code register and the parity is correct, then it is considered a match. When a match is found and if the stop bit is 1, set the event status bit (bit 5 of the PME_STS1 register) to `1' within 100usec of the falling edge of clock 10. The state machine will reset after 11 clocks and the process will restart. The process will continue until it is shut off by setting the SPEKEY_EN bit (see following sub-section). The state machine will reset if there is a period where the clock remains high for more than one keyboard clock period (115-145usec) in the middle of the transmission (i.e., before clock 11). This is to prevent the generation of a false PME. The CLK32_PRSN bit (bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A) will determine the clock source for this feature when the part is powered by VCC. If an external 32kHz clock source is not connected, the 32kHz internal signal is derived from the 14MHz clock when VCC is active. Use the 32kHz clock input or crystal oscillator for this feature when the part is under trickle power. This feature will not work when the part is under trickle power (VCC removed) if an external 32kHz clock source is not connected. The SPEKEY_EN bit at bit 1 of the CLOCKI32 register at 0xF0 in Logical Device A is used to control this feature. This bit is used to turn the logic for this feature on and off. It will disable the 32kHz clock input to the logic. The logic will draw no power when disabled. The bit is defined as follows: 0= "Wake on specific key" logic is on (default) 1= "Wake on specific key" logic is off
Note: The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register at bit 5) when the logic for feature is turned on.
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7.5
System Management Interrupt (SMI)
The LPC47S45x implements a "group" nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists of the enabled interrupts from Super I/O Device Interrupts and many of the GPIOs pins. The GP27/nIO_SMI pin, when selected for the nIO_SMI function, can be programmed to be active high or active low via the polarity bit in the GP27 register. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain output. The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 7. The nSMI output is then enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2 An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows: nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_SMBus and IRQ_SMBus) or (EN_RI1 and IRQ_RI1) or (EN_P12 and IRQ_P12) or (EN_RI2 and IRQ_RI2) Note: The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit respectively.
7.5.1
SMI REGISTERS
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers 3-5. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the control registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit. Status bits for the GPIOs are cleared on a write of `1'. The SMI logic for these events is implemented such that the output of the status bit for each event is combined with the corresponding enable bit in order to generate an SMI. The P12 and P16 bits enable an SMI event on single high-to-low edge or on both high-to-low and low-to-high edges. Default is single edge. There is also a polarity select bit for P12 in the configuration register 0xF0 in logical device 7. The register that selects the edge, Edge Select register, is located at the address programmed in the Base I/O Address register in the Logical Device A at an offset of 21h. Refer also to PME Status and Enable register 2. See the Runtime Registers sections for description on these registers. If both edges are selected for generating an SMI via p16, then the SMI is asserted on each edge until the P16 SMI status bit is cleared. If both edges are selected for generating an SMI via P12, then a short pulse (20ns) is generated on each edge. However, the P12 SMI status bit is set on each edge until cleared. The P12 SMI is not recommended to be used in this mode of operation. Note that P12 and P16 bits are cleared by write of `1'. The SMI generated by P16 is deasserted when the P16 SMI status bit is written to `1'. However, the SMI generated by P12 is cleared at the source. The SMI logic for the P16 event is implemented such that the output of the status bit for the event is combined with the corresponding enable bit in order to generate an SMI. The SMI registers are accessed at an offset from Runtime Registers Block (see Runtime register section for more information). The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these status bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these status bits are not cleared by a write of `1'. The SMI logic for these events is implemented such that each event is directly combined with the corresponding enable bit in order to generate an SMI. See the "Runtime Registers" section for the definition of these registers.
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7.5.2
ACPI SUPPORT REGISTER FOR SMI GENERATION
In addition to the SMI, status and enable, registers, the LPC47S45x has implemented the ACPI PM1 and GPE registers. These registers can be used to generate an SMI event. To generate an SMI event from the PM1/GPE registers: Enable Bit[7] EN_SMI of the SMI_EN2 register at offset 17h Do not enable Bit[0] SCI_EN in the PM1_CNTRL1 register at offset 60h. Set Bit[6] SMI_SCI_ENB to `0' in the PS_CNTRL register, Logical Device A at offset 0xF8. This bit is used to generate an SMI for Enabled SCI event Enable selected SCI events in the PM1 and GPE enable registers. The ACPI PM1 Control register is implemented in the LPC47S45x to allow the generation of an SMI when the SLP_EN bit (PM1_CNTRL2 bit 5) is written to `1'. The SLP_TYPx field (bits[4:2]) is also read/write and is used to define the type of hardware sleep state the system enters when the SLP_EN bit is set to one.. The PM1_CNTRL1 and PM1_CNTRL2 registers implement the ACPI PM1 Control register. These registers are located at the address programmed in the Base I/O address in Logical Device A at the offset of 0x60, 0x61. Software will treat these as a 16-bit register since the two 8-bit registers are adjacent. See the Runtime Registers section for description on these registers.
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8 8.1
RUNTIME REGISTERS Runtime Registers Block Summary
The following registers are runtime registers in the LPC47S45x. They are located at the address programmed in the Base I/O Address in Logical Device A (Runtime Registers Block) at the offset shown. These registers are powered by VTR.
Table 79. Runtime Register Block Summary OFFSET (hex) TYPE PCI RESET VCC POR VTR POR Vbat POR SOFT RESET REGISTER SMBus2 REG OFFSET -
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21
R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R R/W
(Note 6) (Note 6) 0x00 0x03 0x02 0x00 -
(Note 6) (Note 6) 0x00 0x03 0x02 0x00 -
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 (Note 6) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (Note 6) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00
(Note 6) (Note 6) (Note 6) (Note 6) -
PME_STS Reserved PME_EN Reserved PME_STS1 PME_STS2 PME_STS3 PME_STS4 PME_STS5 PME_STS6 PME_EN1 PME_EN2 PME_EN3 PME_EN4 PME_EN5 PME_EN6 SMI_STS 1 SMI_STS 2 SMI_STS3 SMI_STS4 SMI_STS5 SMI_STS6 SMI_EN1 SMI_EN2 SMI_EN3 SMI_EN4 SMI_EN5 SMI_EN6 MSC_STS UART2 FIFO Control Shadow Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow Edge Select Register
Rev. 04-30-07
SMSC LPC47S45x
Page 156 of 259
DATASHEET
OFFSET (hex)
TYPE
PCI RESET
VCC POR
VTR POR
Vbat POR
SOFT RESET
REGISTER
22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
R/W (Note 3) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
-
-
0x00 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x01 0x04 0x01 0xF0 0x00 0x00 0x00 0x00 0x00 0x00
-
-
Device Disable Register GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 GP40 GP41 GP42 GP43 GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GP60 GP61 GP62 GP8 GP1 GP2 GP3 GP4 GP5 GP6
SMBus2 REG OFFSET -
0x00 0x00 (Note 5) (Note 5) 0x00 0x00 (Note 10) (Note 10) (Note 4) (Note 4) (Note 4a) (Note 4a) -
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SMSC LPC47S45x
Page 157 of 259
DATASHEET
OFFSET (hex)
TYPE
PCI RESET
VCC POR
VTR POR
Vbat POR
SOFT RESET
REGISTER
51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76
R/W R/W R/W R/W R/W (Note 1) R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W (Note 1) R R R/W R R/W R R/W R R R R/W R R R R R R R R R R/W
0x00 0x00 0x00 0x00 (Note 2) -
0x00 0x00 0x00 0x00 -
0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 1010 11xxb (Note 9) 0x02
0x00 0x00 0X00 0X00 0X00 0X00 0X00 0X00 0X00 0X00 -
-
GP7 WDT_TIME_OUT WDT_VAL WDT_CFG WDT_CTRL FAN Reserved - read returns 0 Fan Control Fan Tachometer Reserved - read returns 0 Fan Preload Reserved - read returns 0 LED1 LED2 Keyboard Scan Code PM1_CNTRL1 PM1_CNTRL2 Reserved - read returns 0 Reserved - read returns 0 SMI_STS7 Reserved - read returns 0 SMI_EN7 Reserved - read returns 0 PME_STS7 Reserved - read returns 0 Reserved - read returns 0 Reserved - read returns 0 PME_EN7 Vcc_CNT1 Byte 1 (LSB) Vcc_CNT2 Byte 2 Vcc_CNT3 Byte 3 Vcc_CNT4 Byte 4 (MSB) Vtr_CNT1 Byte 1 (LSB) Vtr_CNT2 Byte 2 Vtr_CNT3 Byte 3 Vtr_CNT4 Byte 4 (MSB) Reserved - read returns 0 SMBus2 Slave Address and Enable LPC_ARB Register PM1_STS1 PM1_STS2 Arbitration
SMBus2 REG OFFSET -
04 05 06 07 08 09 0A 0B -
77
R/W (Note 11) R/W R/W
0x02
0x02
-
78 79
-
-
(Note 7) x0xx xxxxb (Note 7a)
0x00 0x00
0000 00x0b (Note 8) -
-
-
SMSC LPC47S45x
Page 158 of 259
Rev. 04-30-07
DATASHEET
OFFSET (hex)
TYPE
PCI RESET
VCC POR
VTR POR
Vbat POR
SOFT RESET
REGISTER
7A 7B 7C 7D 7E 7F
R/W R/W R/W R/W R/W R/W
-
-
(Note 7) (Note 7) 0x00 0x00 -
0x00 0x00 0x00 0x00
-
PM1_EN1 PM1_EN2 GPE1_STS 1 GPE1_STS 2 GPE1_EN 1 GPE1_EN 2
SMBus2 REG OFFSET -
Note: Reserved bits return 0 on read. Note 1: This register contains some bits that are read or write only. Note 2: Bit 0 is not cleared by PCI RESET. Note 3: The Device Disable Register is read-only when GP43 register bit [3:2] = 01 AND the GP43 pin is high, or when bit 1 of the Device Disable Register is `1'. Note 4: Bit [3] of this register is reset (cleared) on VCC POR and PCI Reset (and VTR POR) for fan output default at power-up. Note 4a: Bit [3] of this register is reset (cleared) on VCC POR and PCI Reset (and VTR POR) for TXD2/IRTX output default at power-up. Note 5: Bits [3:2] of the GP43 register are reset (cleared) on VCC POR and PCI Reset (and VTR POR). Note 6: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared. When the parallel port is activated, PINT follows the nACK input. Note 7: This register is powered by VTR and Vbat. It is reset on Vbat POR to a default value of 0x00 Note 7a: This register is powered by VTR and Vbat. It is reset on Vbat POR to a default value of 0x00 and Bit[7] is cleared on a VTR POR Note 8: A soft reset only resets Bit[0] (LPC_REQ) of the LPC_ARB Arbitration Register. Bit[1] will always reflect the current state of the arbitration logic. Note 9: The two LSBs of the VTR POR reset value of the SMBus2 slave address and enable register are determined by the state of the strapping option pins, SADR0 and SADR1, following a VTR power-on-reset. Note 10: Bits[7:0] may be individually reset on Vcc Reset, PCI Reset, and VTR POR if enabled in Logical Device A at offset 0xF6. Note 11: Bit[1] is set/reset by the arbitration logic and Read only by the LPC Bus.
SMSC LPC47S45x
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DATASHEET
8.2
Runtime Registers Block Description
Table 80 - Runtime Registers Block Description
Note: Reserved bits return 0 on read. NAME REG OFFSET (hex) 00 DESCRIPTION
PME_STS Default = 0x00 on VTR POR
(R/W)
PME_EN Default = 0x00 on VTR POR
02 (R/W)
PME_STS1 Default = 0x00 on VTR POR
04 (R/W)
Bit[0] PME_Status = 0 (default) = 1 Set when The chip would normally assert the IO_PME# signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to PME_Status will clear it and cause the The chip to stop asserting IO_PME#, if enabled. Writing a "0" to PME_Status has no effect. Bit[0] PME_En = 0 IO_PME# signal assertion is disabled (default) = 1 Enables The chip to assert IO_PME# signal Bit[7:1] Reserved PME_En is not affected by Vcc POR, SOFT RESET or PCI RESET PME Wake Status Register 1 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] P12 Bit[1] P16 Bit[2] RI1# Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH Bit[7] RI2# The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect.
SMSC LPC47S45x
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DATASHEET
NAME
PME_STS2 Default = 0x00 on VTR POR
REG OFFSET (hex) 05
DESCRIPTION
(R/W)
PME_STS3 Default = 0x00 on VTR POR
06 (R/W)
PME_STS4 Default = 0x00 on VTR POR
07 (R/W)
PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. PME Wake Status Register 3 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. PME Wake Status Register 4 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] GP43 Bit[6] GP60 Bit[7] GP61 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect.
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SMSC LPC47S45x
DATASHEET
NAME
PME_STS5 Default = 0x00 on VTR POR
REG OFFSET (hex) 08
DESCRIPTION
(R/W)
PME_STS6 Default = 0x01 on VTR POR Bit 0 is set to `1' on VCC POR, VTR POR, PCI RESET and SOFT RESET
09 (R/W)
PME Wake Status Register 5 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. This register indicates the state of the individual PME sources, independent of the individual source enables or the PME_En bit. If the PME source has asserted an event, the associated PME Status bit will be a "1". Bit[0] PINT The parallel port interrupt defults to 1 when the parallel port activate bit is cleared. When the parallel port is activated, PINT follows the nACK input. Bit[1] U2INT Bit[2] U1INT Bit[3] FINT Bit[4] MINT Bit[5] KINT Bit[6] WDT Bit[7] SMB The PME Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Status Register has no effect.
SMSC LPC47S45x
Page 162 of 259
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DATASHEET
NAME
PME_EN1 Default = 0x00 on VTR POR
REG OFFSET (hex) 0A
DESCRIPTION
(R/W)
PME_EN2 Default = 0x00 on VTR POR
0B (R/W)
PME Wake Enable Register 1 This register is used to enable individual PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] P12 Bit[1] P16 Bit[2] RI1# Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH Bit[7] RI2# The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. PME Wake Enable Register 2 This register is used to enable individual PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET.
SMSC LPC47S45x
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DATASHEET
NAME
PME_EN3 Default = 0x00 on VTR POR
REG OFFSET (hex) 0C
DESCRIPTION
(R/W)
PME_EN4 Default = 0x00 on VTR POR
0D (R/W)
PME Wake Status Register 3 This register is used to enable individual PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. PME Wake Enable Register 4 This register is used to enable individual PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] GP43 Bit[6] GP60 Bit[7] GP61 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET.
SMSC LPC47S45x
Page 164 of 259
Rev. 04-30-07
DATASHEET
NAME
PME_EN5 Default = 0x00 on VTR POR
REG OFFSET (hex) 0E
DESCRIPTION
(R/W)
PME_EN6 Default = 0x00 on VTR POR
0F (R/W)
SMI_STS1 Default = 0x02 on VTR POR Bit 1 is set to `1' on VCC POR, VTR POR, PCI Reset and soft reset
10 (R/W)
PME Wake Enable Register 5 This register is used to enable individual PME wake sources onto the IO_PME# wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the IO_PME# signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the IO_PME# signal. Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. PME Enable Register 6 This register enables the individual PME sources onto the PME_ST bus. When the enable bit is `1' and the PME source has asserted a wake event, the PME_ST bus is asserted. The PME_ST bus cannot be asserted if the enable bit is `0'. Bit[0] PINT Bit[1] U2INT Bit[2] U1INT Bit[3] FINT Bit[4] MINT Bit[5] KINT Bit[6] WDT Bit[7] SMB SMI Status Register 1 This register is used to read the status of the SMI inputs. The following bits must be cleared at their source. Bit[0] Reserved Bit[1] PINT The parallel port interrupt defults to 1 when the parallel port activate bit is cleared. When the parallel port is activated, PINT follows the nACK input. Bit[2] U2INT Bit[3] U1INT Bit[4] FINT Bit[5] Reserved Bit[6] Reserved Bit[7] WDT
SMSC LPC47S45x
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DATASHEET
NAME
SMI_STS2 Default = 0x00 on VTR POR
REG OFFSET (hex) 11
DESCRIPTION
(R/W)
SMI_STS3 Default = 0x00 on VTR POR
12 (R/W)
SMI_STS4 Default = 0x00 on VTR POR
13 (R/W)
SMI_STS5 Default = 0x00 on VTR POR
14 (R/W)
SMI Status Register 2 This register is used to read the status of the SMI inputs. Bits 2-6 are cleared by a write of 1 to the bit. Bit[0] MINT. Cleared at source. Bit[1] KINT. Cleared at source. Bit[2] SMB Bit[3] RI1# Bit[4] P12. Status bit is cleared by a write of 1. The SMI event is cleared at the source. Bit[5] RI2# Bit[6] Reserved Bit[7] Reserved SMI Status Register 3 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP60 Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27 SMI Status Register 4 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] FAN_TACH Bit[6] GP43 Bit[7] GP61 SMI Status Register 5 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57
SMSC LPC47S45x
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DATASHEET
NAME
SMI_STS6 Default = 0x00 on VTR POR
REG OFFSET (hex) 15
DESCRIPTION
(R/W)
SMI_EN1 Default = 0x00 on VTR POR
16 (R/W)
SMI_EN2 Default = 0x00 on VTR POR
17 (R/W)
SMI_EN3 Default = 0x00 on VTR POR
18 (R/W)
SMI Status Register 6 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 SMI Enable Register 1 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] Reserved Bit[1] EN_PINT Bit[2] EN_U2INT Bit[3] EN_U1INT Bit[4] EN_FINT Bit[5] Reserved Bit[6] Reserved Bit[7] EN_WDT SMI Enable Register 2 This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto the nIO_SMI GPI/O pinor the serial IRQ stream. Unless otherwise noted, 1=Enable 0=Disable Bit[0] EN_MINT Bit[1] EN_KINT Bit[2] EN_SMB Bit[3] EN_RI1# Bit[4] EN_P12 Bit[5] EN_RI2# Bit[6] EN_SMI_S Bit[7] EN_SMI SMI Enable Register 3 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP60 Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27
Page 167 of 259 Rev. 04-30-07
SMSC LPC47S45x
DATASHEET
NAME
SMI_EN4 Default = 0x00 on VTR POR
REG OFFSET (hex) 19
DESCRIPTION
(R/W)
SMI_EN5 Default = 0x00 on VTR POR
1A (R/W)
SMI_EN6 Default = 0x00 on VTR POR
1B (R/W)
SMI Enable Register 4 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] FAN_TACH Bit[6] GP43 Bit[7] GP61 SMI Enable Register 5 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 SMI Enable Register 6 This register enables the individual SMI sources onto the SMI_ST bus. When the enable bit is `1' and the SMI source has asserted an SMI event, the SMI_ST bus is asserted. The SMI_ST bus cannot be asserted if the enable bit is `0'. Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17
SMSC LPC47S45x
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DATASHEET
NAME
MSC_STS Default = 0x00 on VTR POR
REG OFFSET (hex) 1C
DESCRIPTION
(R/W)
UART2 FIFO Control Shadow Default = 0x00 on VCC POR, VTR POR and PCI RESET Force Disk Change Default = 0x03 on VCC POR and PCI RESET
1D (R)
1E (R/W)
Floppy Data Rate Select Shadow Default = 0x02 on VCC POR, VTR POR and PCI RESET
1F (R)
Miscellaneous Status Register Bits[5:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an edge occurs on the GP21 pin. Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an edge occurs on the GP22 pin. Bit[2] Either Edge Triggered Interrupt Input 2 Status. This bit is set when an edge occurs on the GP41 pin. Bit[3] Either Edge Triggered Interrupt Input 3 Status. This bit is set when an edge occurs on the GP43 pin. Bit[4] Either Edge Triggered Interrupt Input 4 Status. This bit is set when an edge occurs on the GP60 pin. Bit[5] Either Edge Triggered Interrupt Input 5 Status. This bit is set when an edge occurs on the GP61 pin. Bit[7:6] Reserved. This bit always returns zero. UART FIFO Control Shadow 2 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Force Change 1 and Force Change 0 can be written to 1 are not clearable by software. Force Change 1 is cleared on (nSTEP AND nDS1) Force Change 0 is cleared on (nSTEP AND nDS0). DSK CHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR (nDS1 AND Force Change 1) OR nDSKCHG. Setting either of the Force Disk Change bits active (1) forces the FDD nDSKCHG input active when the appropriate drive has been selected. Bit[0] Force Change for FDC0 0=Inactive 1=Active Bit[1] Force Change for FDC1 0=Inactive 1=Active Bit[7:2] Reserved, Reads 0 Floppy Data Rate Select Shadow Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 Bit[2] PRECOMP 0 Bit[3] PRECOMP 1 Bit[4] PRECOMP 2 Bit[5] Reserved Bit[6] Power Down Bit[7] Soft Reset
SMSC LPC47S45x
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DATASHEET
NAME
UART1 FIFO Control Shadow Default = 0x00 on VCC POR, VTR POR and PCI RESET Edge Select Register Default = 0x00 on VTR POR
REG OFFSET (hex) 20
DESCRIPTION
(R)
21 (R/W)
UART FIFO Control Shadow 1 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Bit[0] EDGE_P12_SMI 0= P12 SMI status bit is set on the high-to-low edge of P1.2 1= P12 SMI status bit is set on both the high-to-low and low-tohigh edge of P1.2 Bit[1] EDGE_P16_SMI 0= P16 SMI status bit is set on the high-to-low edge of P1.6 1= P16 SMI status bit is set on both the high-to-low and low-tohigh edge of P1.6 Bit[2] EDGE_P12_PME 0= P12 PME status bit is set on the high-to-low edge of P1.2 1= P12 PME status bit is set on both the high-to-low and low-tohigh edge of P1.2 Bit[3] EDGE_P16_PME 0= P16 PME status bit is set on the high-to-low edge of P1.6 1= P16 PME status bit is set on both the high-to-low and low-tohigh edge of P1.6 Bits[7:4] Reserved
SMSC LPC47S45x
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DATASHEET
NAME
Device Disable Register Default = 0x00 VTR POR
REG OFFSET (hex) 22
DESCRIPTION
Read/Write when GP43 register bits[3:2] = 01 AND GP43 pin = 0 OR GP43 register bits[3:2] 01 (Device Disable Register Bit[1] must be 0)
If "0" (enabled), bits[7:3] have no effect on the devices; devices are controlled by their respective activate bits. If "1" (disabled), bits[7:3] override the activate bits in the configuration registers for each logical block. Bit[0] Floppy Write Protect. 0= no effect: floppy write protection is controlled by the write protect pin or the Forced Write Protect bit (bit 0 of register 0xF1 in Logical Device 0); 1= Write Protected. If set to 1, this bit overrides the write protect pin on the part and the forced write protect bit.
nWRTPRT (to the FDC Core) = WP (FDC SRA Register, Bit 1) = (Floppy Write Protect) OR nWRTPRT(from the FDD Interface) OR (nDS0 AND Force Write Protect ) OR (nDS1 AND Force Write READ-ONLY Protect ). When GP43 Note: The Force Write Protect bit is in the FDD Option register bits[3:2] Configuration register. =01 AND GP43 pin = 1 Bit[1] Register Lock OR This bit is cleared on VCC POR and PCI Reset. Device Disable 0 - No effect (Default) Register 1 - All of the bits in this register are Read Only until a VCC POR or Bit[1]=1 PCI RESET. Bits[2] Reserved. Return 0 on read. Bit[3]: Floppy Enable. 0=No effect: FDC controlled by its activate bit; 1=Floppy Disabled Bit[4] Reserved Bit[5] Serial Port 2 Enable 0=No effect: UART2 controlled by its activate bit; 1=UART2 Disabled Bit[6] Serial Port 1 Enable. 0=No effect: UART1 controlled by its activate bit; 1=UART1 Disabled Bit[7] Parallel Port Enable. 0=No effect: PP controlled by its activate bit; 1=PP Disabled
Note: Any peripheral that is disabled in this register will not be accessible by either the LPC interface or the SMBus. See Table 74.
SMSC LPC47S45x
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DATASHEET
NAME
GP10 Default = 0x04 on VTR POR
REG OFFSET (hex) 23
DESCRIPTION
(R/W)
GP11 Default = 0x04 on VTR POR
24 (R/W)
GP12 Default = 0x04 on VTR POR
25 (R/W)
GP13 Default = 0x04 on VTR POR
26 (R/W)
GP14 Default = 0x04 on VTR POR
27 (R/W)
General Purpose I/0 bit 1.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD0 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD1 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD3 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD4 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
SMSC LPC47S45x
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DATASHEET
NAME
GP15 Default = 0x04 on VTR POR
REG OFFSET (hex) 28
DESCRIPTION
(R/W)
GP16 Default = 0x04 on VTR POR
29 (R/W)
GP17 Default = 0x04 on VTR POR
2A (R/W)
GP20 Default = 0x01 on VTR POR
2B (R/W)
General Purpose I/0 bit 1.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD5 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD6 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=XD7 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=nDS1 - Floppy Drive select 1 (Note 3) 01=8042 P17 function (User Note 2) 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
SMSC LPC47S45x
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DATASHEET
NAME
GP21 Default =0x01 on VTR POR
REG OFFSET (hex) 2C
DESCRIPTION
(R/W)
GP22 Default =0x01 on VTR POR
2D (R/W)
GP23 Default=0x01 on VTR POR
2E (R/W)
GP24 Default = 0x01 on VTR POR
2F (R/W)
General Purpose I/0 bit 2.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Interrupt Input 0 (Note 1) 01=8042 P16 function (User Note 2) 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11= nMRT1 - floppy motor select 1 (Note 3) 10= Either Edge Triggered Interrupt Input 1 (Note 1) 01=8042 P12 function (User Note 2) 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= IRQIND (IRQ Input D) 0= Basic GPIO Function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=P17 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
SMSC LPC47S45x
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DATASHEET
NAME
GP25 Default = 0x01 on VTR POR
REG OFFSET (hex) 30
DESCRIPTION
(R/W)
GP26 Default = 0x01 on VTR POR
31 (R/W)
GP27 Default = 0x01 on VTR POR
32 (R/W)
GP30 Default = 0x01 on VTR POR
33 (R/W)
GP31 Default = 0x01 on VTR POR
34 (R/W)
General Purpose I/0 bit 2.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= 8042 P12 function (User Note 2) 0= Basic GPIO Function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=IO_SMI# (Note 4) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nXCS2 (X-Bus Chip Select 2) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nXCS3 (X-Bus Chip Select 3) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
SMSC LPC47S45x
Page 175 of 259
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DATASHEET
NAME
GP32 Default = 0x01 on VTR POR
REG OFFSET (hex) 35
DESCRIPTION
(R/W)
GP33 Default = 0x01 on VTR POR Default = 0x00 on VCC POR and PCI Reset (Note 2) GP34 Default = 0x01 on VTR POR
36 (R/W)
37 (R/W)
GP35 Default = 0x01 on VTR POR
38 (R/W)
GP36 Default = 0x01 on VTR POR
39 (R/W)
General Purpose I/0 bit 3.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= FAN_TACH 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=IRQINA (IRQ Input A) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=IRQINB (IRQ Input B) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nKBDRST 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
SMSC LPC47S45x
Page 176 of 259
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DATASHEET
NAME
GP37 Default = 0x01 on VTR POR
REG OFFSET (hex) 3A
DESCRIPTION
(R/W)
GP40 Default =0x01 on VTR POR
3B (R/W)
GP41 Default =0x01 on VTR POR
3C (R/W)
GP42 Default =0x01 on VTR POR
3D (R/W)
General Purpose I/0 bit 3.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=A20M 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 4.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=DRVDEN0 (Note 3) 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 4.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Interrupt Input 2 01=DRVDEN1 (Note 3) 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 4.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=IO_PME# Note: Configuring this pin function as output with non-inverted polarity will give an active low output signal. The output type can be either open drain or push-pull. 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
SMSC LPC47S45x
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DATASHEET
NAME
GP43 Default = 0x01 on VTR POR Bits[3:2] are reset (cleared) on VCC POR, VTR POR and PCI Reset
REG OFFSET (hex) 3E
DESCRIPTION
(R/W)
GP50 Default = 0x01 on VTR POR
3F (R/W)
GP51 Default = 0x01 on VTR POR
40 (R/W)
GP52 Default = 0x01 on VTR POR
41 (R/W)
General Purpose I/0 bit 4.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Either Edge Triggered Interrupt Input 3 10=Reserved 01=Device Disable Register Control. The GP43 pin is an input, with non-inverted polarity. When bits[3:2]=01, they cannot be changed by writing to these bits; they are cleared by VCC POR, PCI Reset and VTR POR. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a VCC POR, PCI Reset or VTR POR. The Device Disable register is controlled by the value of the GP43 pin as follows: If the GP43 pin is high, the Device Disable Register is Read-Only. If the GP43 pin is low, the Device Disable Register is Read/Write. 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= RI2# (User Note 1) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nDCD2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=IRRX (Note 6) 01=RXD2 (Note 6) 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
Page 178 of 259 Rev. 04-30-07
SMSC LPC47S45x
DATASHEET
NAME
GP53 Default = 0x00 on VTR POR, VCC POR and PCI RESET (Note 2)
REG OFFSET (hex) 42
DESCRIPTION
(R/W)
GP54 Default = 0x01 on VTR POR
43 (R/W)
GP55 Default = 0x01 on VTR POR
44 (R/W)
GP56 Default = 0x01 on VTR POR
45 (R/W)
GP57 Default = 0x01 on VTR POR
46 (R/W)
General Purpose I/0 bit 5.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=IRTX (Note 5) 01=TXD2 (Note 5) 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nDSR2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nRTS2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nCTS2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nDTR2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
Page 179 of 259 Rev. 04-30-07
SMSC LPC47S45x
DATASHEET
NAME
GP60 Default = 0x01 on VTR POR
REG OFFSET (hex) 47
DESCRIPTION
(R/W)
GP61 Default = 0x04 on VTR POR (Note 6)
48 (R/W)
GP62 Default = 0x01 on VTR POR
49 (R/W)
GP8 Default = 0xF0 on VTR POR Bits[7:0] may be individually reset on VCC Reset, PCI Reset, and VTR POR if enabled in Logical Device A at offset 0xF6
4A (R/W)
General Purpose I/0 bit 6.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Interrupt Input 4 (Note 1) 01=LED1 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Interrupt Input 5 01=LED2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=IRQINC (IRQ Input C) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 Data Register 8 Bit[0] GP80 Bit[1] GP81 Bit[2] GP82 Bit[3] GP83 Bit[4] GP84 Bit[5] GP85 Bit[6] GP86 Bit[7] GP87
Note: Pins GP80 to GP87 default to outputs on VTR POR. See Table 94.
SMSC LPC47S45x
Page 180 of 259
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DATASHEET
NAME
GP1 Default = 0x00 on VTR POR
REG OFFSET (hex) 4B
DESCRIPTION
(R/W)
GP2 Default = 0x00 on VTR POR
4C (R/W)
GP3 Default = 0x00 on VTR POR Bits 3 is reset on VCC POR, PCI Reset and VTR POR GP4 Default = 0x00 on VTR POR
4D (R/W)
4E (R/W)
GP5 Default = 0x00 on VTR POR Bit[3] is reset on VTR POR, VCC POR and PCI RESET GP6 Default = 0x00 on VTR POR
4F (R/W)
50 (R/W)
General Purpose I/0 Data Register 1 Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 General Purpose I/0 Data Register 2 Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27 General Purpose I/0 Data Register 3 Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP34 Bit[5] GP35 Bit[6] GP36 Bit[7] GP37 General Purpose I/0 Data Register 4 Bit[0] GP40 Bit[1] GP41 Bit[2] GP42 Bit[3] GP43 Bit[7:4] Reserved General Purpose I/0 Data Register 5 Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 General Purpose I/0 Data Register 6 Bit[0] GP60 Bit[1] GP61 Bit[2] GP62 Bit[7-3] Reserved
SMSC LPC47S45x
Page 181 of 259
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DATASHEET
NAME
GP7 Default = 0x00 on VTR POR
REG OFFSET (hex) 51
DESCRIPTION
(R/W)
WDT_TIME_OUT Default = 0x00 on VCC POR, VTR POR, and PCI Reset
52 (R/W)
WDT_VAL Default = 0x00 on VCC POR, VTR POR, and PCI Reset
53 (R/W)
WDT_CFG Default = 0x00 on VCC POR, VTR POR, and PCI Reset
54 (R/W)
General Purpose I/0 Data Register 7 Bit[0] GP70 Bit[1] GP71 Bit[2] GP72 Bit[3] GP73 Bit[4] GP74 Bit[5] GP75 Bit[6] GP76 Bit[7] GP77 Watch-dog Timeout Bit[0] Reserved Bit[1] Reserved Bits[6:2] Reserved, = 00000 Bit[7] WDT Time-out Value Units Select = 0 Minutes (default) = 1 Seconds Watch-dog Timer Time-out Value Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of WDT_TIME_OUT register (0x52). 0x00 Time out disabled 0x01 Time-out = 1 minute (second) ......... 0xFF Time-out = 255 minutes (seconds) Watch-dog timer Configuration Bit[0] Joy-Stick Enable =1 WDT is reset upon an I/O read or write of Port 201h =0 WDT is not affected by I/O reads or writes to Port 201h. Bit[1] Keyboard Enable =1 WDT is reset upon a Keyboard interrupt. =0 WDT is not affected by Keyboard interrupts. Bit[2] Mouse Enable =1 WDT is reset upon a Mouse interrupt. =0 WDT is not affected by Mouse interrupts. Bit[3] Reserved Bits[7:4] WDT Interrupt Mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable
SMSC LPC47S45x
Page 182 of 259
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DATASHEET
NAME
WDT_CTRL Default = 0x00 on VCC POR and VTR POR Default = 0000000xb on PCI Reset Note: Bit[0] is not cleared by PCI Reset
REG OFFSET (hex) 55
DESCRIPTION
(R/W) Bit[2] is Write-Only
FAN Default = 0x00 on VTR POR
56 (R/W)
Fan Control Default = 0x10 on VTR POR
58 (R/W)
Watch-dog timer Control Bit[0] Watch-dog Status Bit, R/W =1 WD timeout occurred =0 WD timer counting Bit[1] Reserved Bit[2] Force Timeout, W =1 Forces WD timeout event; this bit is self-clearing Bit[3] P20 Force Timeout Enable, R/W =1 Allows rising edge of P20, from the Keyboard Controller, to force the WD timeout event. A WD timeout event may still be forced by setting the Force Timeout Bit, bit 2. =0 P20 activity does not generate the WD timeout event. Note: The P20 signal will remain high for a minimum of 1us and can remain high indefinitely. Therefore, when P20 forced timeouts are enabled, a self-clearing edge-detect circuit is used to generate a signal which is ORed with the signal generated by the Force Timeout Bit. Bit[7:4] Reserved. Set to 0 FAN Register Bit[0] Fan Control 1=FAN pin is high 0=bits[6:1] control the duty cycle of the FAN pin. Bit[6:1] Duty Cycle Control Control the duty cycle of the FAN pin 000000 = pin is low 100000 = 50% duty cycle 111111 = pin is high for 63, low for 1 Bit[7] Fan Clock Select This bit is used with the Fan Clock Source Select and the Fan Clock Multiplier bits in the Fan Control register (0x58) to determine the fan speed FOUT. See Different Modes for Fan in Table 61 on page 124 in "Fan Speed Control and Monitoring" section. The fan speed may be doubled through bit 2 of Fan Control Register at 0x58. Fan Control Register Bit[0] Fan Clock Source Select This bit and the Fan Clock Multiplier bit is used with The Fan Clock Select bit in the Fan register (0x56) to determine the fan speed FOUT. See Different Modes for Fan in Table 61 on page 124 in "Fan Speed Control and Monitoring" section. Bit[1] Reserved Bit[2] Fan Clock Multiplier 0=No multiplier used 1=Double the fan speed selected by bit 0 of this register and bit 7 of the Fan register Bit[3] Reserved Bit[5:4] FAN Count Divisor. Clock scalar for adjusting the tachometer count. Default = 2. 00: divisor = 1 01: divisor = 2 10: divisor = 4 11: divisor = 8 Bit[7:6] Reserved
Page 183 of 259 Rev. 04-30-07
SMSC LPC47S45x
DATASHEET
NAME
Fan Tachometer Register Default = 0x00 on VTR POR Fan Preload Register Default = 0x00 on VTR POR LED1 Default = 0x00 on VTR POR
REG OFFSET (hex) 59
DESCRIPTION
(R)
5B (R/W) 5D (R/W)
Fan Tachometer Register Bit[7:0] The 8-bit FAN tachometer count. The number of counts of the internal clock per pulse of the fan. The count value is computed from Equation 1 in the Fan section. This value is the final (maximum) count of the previous pulse (latched). The value in this register may not be valid for up to 2 pulses following a write to the preload register. Fan Preload Register Bit[7:0] The FAN tachometer preload. This is the initial value used in the computation of the FAN count. Writing this register resets the tachometer count. Bit[1:0] LED1 Control 00=off 01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=Blink at 1/2 HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on Bits[7:2] Reserved Bit[1:0] LED2 Control 00=off 01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=Blink at 1/2 Hz rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on Bits[7:2] Reserved Keyboard Scan Code Bit[0] LSB of Scan Code ... ... ... Bit[7] MSB of Scan Code Power Management 1 Control Register 1 (PM1_CNTRL 1) Bit[0] SCI_EN When this bit is set, then the enabled PM1 and GPE1 power management events will generate an nIO_PME interrupt. When this bit is reset power management events will not generate an nIO_PME interrupt. Instead, it will generate an SMI if the SMI_SCI_EN bit is cleared. This bit does not affect the power button or RTC wakeup event. This bit also does not affect GPE1 wakeup events.
LED2 Default = 0x01 on VTR POR
5E (R/W)
Keyboard Scan Code Default = 0x00 on VTR POR PM1_CNTRL1 Default = 0x00 on Vbat POR
5F (R/W)
60 R/W
Bits[7:1] Reserved. These bits always return a value 0.
SMSC LPC47S45x
Page 184 of 259
Rev. 04-30-07
DATASHEET
NAME
PM1_CNTRL2 Default = 0x00 on Vbat POR
REG OFFSET (hex) 61
DESCRIPTION
Bits[1:0] Read-Only, reads always return 0
R/W Bit[5] is Write-Only Bits[4:2] SLP_TYPx This 3-bit field defines the type of hardware sleep state the system enters when the SLP_EN bit is set to one. When bits 4:2=111 or 110 (S4, S5) the LPC47S45x will transition the machine to the off state when the SLP_EN bit is set to one. That is, with this field set to 111 or 110, nPS_ON will go inactive (float) after a 1-2 RTC clock delay when SLP_EN is set. This delay is a minimum of one 32kHz clock and a maximum of two 32kHz clocks (31.25sec-62.5sec). When this field is any other value, there is no effect.
Bit[5] SLP_EN This is a write-only bit and reads to it always return a zero. Writing a `1' to this bit causes the system to sequence into the sleeping state associated with the SLP_TYPx fields after a 1-2 RTC clock delay, if the SLP_CTRL bit in the Power Supply Control register is cleared. If the SLP_CTRL bit is set, do not sequence into the sleeping state associated with the SLP_TYPx field, but generate an SMI. Note: the SLP_EN_SMI bit in the SMI Status Register 7 is always set upon writing a `1' to the SLP_EN bit. Writing a `0' to this bit has no effect. Bits[7:6] Read-Only, reads always return 0 SMI Status Register 7 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP34 Bit[1] GP35 Bit[2] GP36 Bit[3] GP37 Bit[4] P16 Bit[5] SLP_EN_SMI This bit is the SMI status bit for writing `1' to bit 5 of the PM1_CNTRL2 register. This bit is set upon writing `1' to bit 5 of the PM1_CNTRL2 register. Bit[6] Reserved Bit[7] GP62 SMI Enable Register 7 This register is used to enable the different interrupt sources onto the group nSMI output. Bit[0] GP34 Bit[1] GP35 Bit[2] GP36 Bit[3] GP37 Bit[4] P16 Bit[5] SLP_EN_SMI Bit[6] Reserved Bit[7] GP62
SMI_STS7 Default = 0x00 on VTR POR
64 (R/W)
SMI_EN7 Default = 0x00 on VTR POR
66 (R/W)
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NAME
PME_STS7 Default = 0x00 on VTR POR
REG OFFSET (hex) 68
DESCRIPTION
(R/W)
PME_EN7 Default = 0x00 on VTR POR
6C (R/W)
Vcc_CNT1 Default = 0x00 on Vbat POR
6D (Read Only) (Note 7)
This register indicates the state of the individual PME sources, independent of the individual source enables or the PME_En bit. If the PME source has asserted an event, the associated PME Status bit will be a "1". Bit[0] GP34 Bit[1] GP35 Bit[2] GP36 Bit[3] GP37 Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] GP62 The PME Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[4:0] will clear it. Writing a "0" to any bit in PME Status Register has no effect. PME Enable Register 7 This register is used to enable individual PME wake sources onto the IO_PME# wake bus. Bit[0] GP34 Bit[1] GP35 Bit[2] GP36 Bit[3] GP37 Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] GP62 Vcc_CNT1 (Byte 1) This register contains the Least Significant Byte (LSB) of the 32 bit VCC Power On Elapsed Time Counter. Bit[7:0] = Bit[7:0] of the 32-bit VCC Power-On-Elapsed-Time Counter Vcc_CNT2 (Byte 2) Bit[7:0] = Bit[15:8] of the 32-bit VCC Power-On-Elapsed-Time Counter Vcc_CNT3 (Byte 3) Bit[7:0] = Bit[23:16] of the 32-bit VCC Power-On-Elapsed-Time Counter Vcc_CNT4 (Byte 4) This register contains the Most Significant Byte (MSB) of the 32 bit VCC Power On Elapsed Time Counter. Bit[7:0] = Bit[31:24] of the 32-bit VCC Power-On-Elapsed-Time Counter Vtr_CNT1 (Byte 1) This register contains the Least Significant Byte (LSB) of the 32 bit VTR Power On Elapsed Time Counter. Bit[7:0] = Bit[7:0] of the 32-bit VTR Power-On-Elapsed-Time Counter
Vcc_CNT2 Default = 0x00 on Vbat POR Vcc_CNT3 Default = 0x00 on Vbat POR Vcc_CNT4 Default = 0x00 on Vbat POR
6E (Read Only) (Note 7) 6F (Read Only) (Note 7) 70 (Read Only) (Note 7)
Vtr_CNT1 Default = 0x00 on Vbat POR
71 (Read Only) (Note 7)
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NAME
Vtr_CNT2 Default = 0x00 on Vbat POR Vtr_CNT3 Default = 0x00 on Vbat POR Vtr_CNT4 Default = 0x00 on Vbat POR
REG OFFSET (hex) 72
DESCRIPTION
Vtr_CNT2 (Byte 2) Bit[7:0] = Bit[15:8] of the 32-bit VTR Power-On-Elapsed-Time Counter Vtr_CNT3 (Byte 3) Bit[7:0] = Bit[23:16] of the 32-bit VTR Power-On-Elapsed-Time Counter Vtr_CNT4 (Byte 4) This register contains the Most Significant Byte (MSB) of the 32 bit VTR Power On Elapsed Time Counter.
(Read Only) (Note 7) 73 (Read Only) (Note 7) 74 (Read Only) (Note 7)
Bit[7:0] = Bit[31:24] of the 32-bit VTR Power-On-Elapsed-Time Counter 76 SMBus2 Slave Bit [0] = Slave Address Bit 0 (Determined by state of the SADR0 Address and Enable on VTR power-up.) Bit [1] = Slave Address Bit 1 (Determined by state of the SADR1 (R/W) on VTR power-up.) Default = 101011xxb Bit [2] = Slave Address Bit 2 on VTR POR, Bit [3] = Slave Address Bit 3 where xx is Bit [4] = Slave Address Bit 4 determined by SADR[1:0] Bit [5] = Slave Address Bit 5 Bit [6] = Slave Address Bit 6 Bit [7] = SMBus2 Enable 0 = SMBus2 Controller Disabled 1 = SMBus2 Controller Enabled When Bit 7 = 0, the SMBus2 controller will not respond to addresses decoded on SDAT or drive SDAT or SCLK. LPC_ARB 77 Bit [0] = LPC X-Bus Access Request (LPC_REQ) Arbitration Register Bit [1] = LPC X-Bus Access Grant (LPC_GNT) Bit 0 is R/W by Bit [2] = Reserved the LPC Bus, Bit [3] = Reserved Default = 0x02 on VTR POR, VCC Bit 1 is set/reset Bit [4] = Reserved by the POR, PCI Reset Bit [5] = Reserved arbitration logic, Default = 000000x0b and Read only Bit [6] = Reserved on Bit [7] = Reserved by the LPC Soft Reset (Note 9) Bus. PM1_STS1 78 Power Management 1 Status Register 1 (PM1_STS 1) Default = 0x00 on Vbat POR PM1_STS2 (Note 8) Default = 0x00 on Vbat POR Bit 7 cleared on VTR POR. (R/W) 79 (R/W) Bit[7:0] = Reserved. These bits always return a value of zero. Power Management 1 Status Register 2 (PM1_STS 2) Bit[0] PWRBTN_STS This bit is set when the nPB_IN signal is asserted. While PWRBTN_EN and PWRBTN_STS are both set an nIO_PME event is raised. In the soft off state (nPS_ON float), a wake-up event (nPS_ON transitions to active low) is generated regardless of the setting of PWRBTN_EN. This bit is only set by hardware and is reset by software writing a one to this bit position, and by Vbat POR. Writing a 0 has no effect.
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DATASHEET
NAME
REG OFFSET (hex)
DESCRIPTION
It is also reset as follows: If the nPB_IN signal is held asserted for more than four seconds, then this bit is cleared, the PWRBTNOR_STS bit is set and the system will transition into the soft off state (nPS_ON floats). Bit[1] Reserved Bit[2] RTC_STS This bit is set when the RTC generates an alarm. Additionally if the RTC_EN bit is set then the setting of the RTC_STS bit will generate a an nIO_PME; if the power supply is `off', it will also cause a wakeup event. When the AL_REM_EN bit is set in the RTC control register 1, then the RTC_STS bit is set due to an RTC alarm event occurring when VTR is not present. This will indicate to the OS the cause of the wakeup event (nPS_ON pin asserted when VTR returns) caused by the "alarm remember" logic in the Soft Power Management block. The "alarm remember " event will cause a wakeup event when VTR returns if the RTC_STS bit is set. This bit is only set by hardware and can only be reset by software writing a one to this bit position and by Vbat POR. Writing a zero has no effect. This wakeup event is blocked when a power button override event occurs (PWRBTNOR_STS bit set). Bit[3] PWRBTNOR_STS This bit is set when the power switch over-ride function is set: If the nPB_IN signal is held asserted for more than four seconds. In this case, the nPS_ON signal floats. Hardware is also required to reset the PWRBTN_STS when issuing a power switch over-ride function. This bit is set by hardware and can only be cleared by software writing a one to this bit position and by Vbat POR. Writing a 0 has no effect. When this bit is set, only the power button can wake the system; all other wakeup events are blocked. This bit must be cleared for other wake events to function. Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] WAK_STS This bit is not set if the WAK_CTRL bit in the power supply control register is cleared. If the nPS_ON pin is made to float as a result of setting the SLP_EN bit, and the WAK_CTRL bit is set, then any enabled wakeup event will set the WAK_STS bit. If the nPS_ON pin is made to float by any other means (i.e., power button override event or power loss) then this bit is not set on return of power. Cleared by software writing a one to this bit position and by VTR POR and Vbat POR.
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DATASHEET
NAME
PM1_EN 1 Default = 0x00 on Vbat POR PM1_EN 2 Default = 0x00 on Vbat POR
REG OFFSET (hex) 7A
DESCRIPTION
Power Management 1 Enable Register 1 (PM1_EN 1) Bit[7:0] = Reserved. These bits always return a value of zero. Power Management 1 Enable Register 2 (PM1_EN 2) Bit[0] PWRBTN_EN This bit is used to enable the assertion of the nPB_IN to generate a event. The PWRBTN_STS bit is set anytime the nPB_IN signal is asserted. The enable bit does not have to be set to enable the setting of the PWRBTN_STS bit by the assertion of the nPB_IN signal. A wake-up event (nPS_ON transitions to active low) is generated regardless of the setting of PWRBTN_EN. Bit[1] Reserved Bit[2] RTC_EN This bit is used to enable the setting of the RTC_STS bit to generate an PME and wake event. The RTC_STS bit is set anytime the RTC generates an alarm. If the RTC_EN bit is not set, then setting the RTC_STS bit will not generate a PME or wake event. Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved
(R/W) 7B (R/W)
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NAME
GPE1_STS 1 Default = 0x00 on VTR POR
REG OFFSET (hex) 7C
DESCRIPTION
General Purpose Event 1 Status Register 1 (GPE1_STS 1) Bit[0] GP23_STS GP23 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[1] GP34_STS GP34 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[2] GP35_STS GP35 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[3] KDAT_STS KBD event status (high-to-low edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[4] MDAT_STS Mouse event status (high-to-low edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[5] SPEKEY_STS SPEKEY event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[6] nRI1_STS RI1 event status (high-to-low edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[7] ALL_PME_STS ALL_PME event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect.
(R/W)
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NAME
GPE1_STS 2 Default = 0x00 on VTR POR
REG OFFSET (hex) 7D
DESCRIPTION
General Purpose Event 1 Status Register 2 (GPE1_STS 2) Bit[0] GP50_STS GP50/RI2 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[1] GP51_STS GP51 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[2] GP52_STS GP52 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[3] GP53_STS GP53 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[4] GP54_STS GP54 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[5] GP55_STS GP55 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[6] GP56_STS GP56 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect. Bit[7] GP57_STS GP57 event status (low-to-high edge with non inverted polarity). 1= event occurred, 0= event did not occur. This bit is cleared by software writing a one to this bit position and by VTR POR. Writing a 0 has no effect.
(R/W)
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DATASHEET
NAME
GPE1_EN 1 Default = 0x00 on Vbat POR
REG OFFSET (hex) 7E
DESCRIPTION
General Purpose Event 1 Enable Register 1 (GPE1_EN 1) Bit[0] GP23_EN GP23 wakeup event enable. 1= enable, 0= disable Bit[1] GP34_EN GP34 wakeup event enable. 1= enable, 0= disable Bit[2] GP35_EN GP35 wakeup event enable. 1= enable, 0= disable Bit[3] KDAT_EN KBD wakeup event enable. 1= enable, 0= disable Bit[4] MDAT_EN Mouse wakeup event enable. 1= enable, 0= disable Bit[5] SPEKEY_EN SPEKEY wakeup event enable. 1= enable, 0= disable Bit[6] nRI1_EN RI1 wakeup event enable. 1= enable, 0= disable Bit[7] ALL_PME_EN ALL_PME wakeup event enable. 1=enable, 0=disable General Purpose Event 1 Enable Register 2 (GPE1_EN 2) Bit[0] GP50_EN GP50/RI2 event enable. 1= enable, 0= disable Bit[1] GP51_EN GP51 event enable. 1= enable, 0= disable Bit[2] GP52_EN GP52 event enable. 1= enable, 0= disable Bit[3] GP53_EN GP53 event enable. 1= enable, 0= disable Bit[4] GP54_EN GP54 event enable. 1= enable, 0= disable Bit[5] GP55_EN GP55 event enable. 1= enable, 0= disable Bit[6] GP56_EN GP56 event enable. 1= enable, 0= disable Bit[7] GP57_EN GP57 event enable. 1= enable, 0= disable
R/W
GPE1_EN 2 Default = 0x00 on Vbat POR
7F R/W
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DATASHEET
User Note 1: If this pin is used for Ring Indicator wakeup, either the RI2# event can be enabled via bit 1 in the PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register. User Note 2: In order to use the P12, P16 and P17 functions, the corresponding GPIO must be programmed for output, non-invert, and push-pull output type. The P12 function should not be selected on GP21 and GP 22 simultaneously. If P12 is selected on GP21 and GP22, simultaneously, then P12 will function on GP22, not on GP21. The P17 function should not be selected on GP20 and GP 62 simultaneously. If P17 is selected on GP20 and GP62, simultaneously, then P17 will function on GP62, not on GP20. Note 1: If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set the PME, SMI and MSC status bits. Note 2: These pins default to an output and LOW on VCC POR and PCI Reset. Note 3: If the FDC function is selected on this pin (MTR1#, DS1#, DRVDEN0, DRVDEN1) then bit 6 of the FDD Mode Register (Configuration Register 0xF0 in Logical Device 0) will override bit 7 in the GPIO Control Register. Bit 7 of the FDD Mode Register will also affect the pin if the FDC function is selected. Note 4: The IO_SMI# pin is inactive when the internal group SMI signal is inactive and when the SMI enable bit (EN_SMI, bit 7 of the SMI_EN2 register) is `0'. When the output buffer type is OD, IO_SMI# pin is floating when inactive; when the output buffer type is push-pull, the IO_SMI# pin is high when inactive. Note 5: If GP52 and GP53 are programmed for RXD2 and TXD2 functions and Serial Port 2 is programmed for IR operation, then these pins will have IR functionality and when serial port 2 is disabled, the TXD2 pin will TRISTATE. If these pins are programmed for IRRX and IRTX then these pins will have IR functionality and when serial port 2 is disabled, the IRTX pin will go to its inactive state. Note 6: The GP61 pin defaults to the LED function active (blinking at a 1 Hz rate, 50% duty cycle) on initial power up (as long as the 32 kHz clock input is active). Note 7: When Byte 1 (LSB) is read, by the LPC Bus or SMBus, Bytes 2 through 4 are latched for eventual read. It is required the counter (Bytes 1 through 4) be read LSB to MSB. Latching of bytes for read output will not affect continued counting Note 8: In the present implementation of nPB_IN, pressing the button will always wake the machine (i.e., activate nPS_ON). Note 9: A soft reset only resets Bit[0] (LPC_REQ). Bit[1] will always reflect the current state of the arbitration logic.
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DATASHEET
9
CONFIGURATION
The Configuration of the LPC47S45x is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47S45x is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the LPC47S45x allows the BIOS to assign resources at POST.
9.1
System Elements
Primary Configuration Address Decoder
After a PCI Reset (PCI_RESET# pin asserted) or VCC Power On Reset the LPC47S45x is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47S45x into Configuration Mode. The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the LPC47S45x is in Configuration Mode. The SYSOPT pin is latched on the falling edge of the PCI_RESET# or on VCC Power On Reset to determine the configuration register's base address. The SYSOPT pin is used to select the CONFIG PORT's I/O address at powerup. Once powered up the configuration port base address can be changed through configuration registers CR26 and CR27. The SYSOPT pin is a hardware configuration pin which is shared with the GP24 signal on pin 45. Note. An external pull-down resistor is required for the base IO address to be 0x02E for configuration. An external pull-up resistor is required to move the base IO address for configuration to 0x04E. The INDEX and DATA ports are effective only when the chip is in the Configuration State.
SYSOPT= 0 10k PULL-DOWN RESISTOR SYSOPT= 1 10K PULL-UP RESISTOR
PORT NAME CONFIG PORT (Note 1) INDEX PORT (Note 1) DATA PORT
0x02E 0x02E INDEX PORT + 1
0x04E 0x04E
TYPE Write Read/Write Read/Write
Note 1: The configuration port base address can be relocated through CR26 and CR27. Entering the Configuration State
The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0x55>
Exiting the Configuration State
The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0xAA>
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9.2
1. 2. 3.
Configuration Sequence
Enter Configuration Mode Configure the Configuration Registers Exit Configuration Mode.
To program the configuration registers, the following sequence must be followed:
Enter Configuration Mode To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Configuration State (The auto Config ports are enabled). Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1.
The desired configuration registers are accessed in two steps: a) b) Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT. Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT.
Note: If accessing the Global Configuration Registers, step (a) is not required.
Exit Configuration Mode To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State.
9.3
Programming Example
OUT DX,AL;Point to Logical Device 8
The following is an example of a configuration program in Intel 8086 assembly language.
;----------------------------. ; ENTER CONFIGURATION MODE | ;----------------------------' MOV DX,02EH MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;----------------------------' MOV DX,02EH MOV AL,07H OUT DX,AL ;Point to LD# Config Reg MOV DX,02FH MOV AL, 08H ; MOV DX,02EH MOV AL,E0H OUT DX,AL ; Point to CRE0 MOV DX,02fH MOV AL,02H OUT DX,AL ; Update CRE0 ;-----------------------------. ; EXIT CONFIGURATION MODE | ;-----------------------------' MOV DX,02EH MOV AX,0AAH OUT DX,AL
Notes: PCI RESET: PCI_RESET# pin asserted SOFT RESET: Bit 0 of Configuration Control register set to one All host accesses are blocked for 500s after VCC POR (see Power-up Timing Diagram)
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DATASHEET
Table 81 - LPC47S45x Configuration Registers Summary INDEX TYPE SOFT CONFIGURATION RESET REGISTER GLOBAL CONFIGURATION REGISTERS 0x00 0x00 0x00 Config Control Reserved - reads return 0 0x00 0x00 0x00 0x00 Logical Device Number 0x62 0x62 0x62 0x62 Device ID - hard wired Current Revision Device Rev - hard wired 0x00 0x00 0x00 0x00 Power Control 0x00 0x00 0x00 Power Mgmt 0x04 0x04 0x04 OSC Sysopt=0: Sysopt=0: Configuration Port Address 0x2E 0x2E Byte 0 Sysopt=1: Sysopt=1: (Low Byte) 0x4E 0x4E Sysopt=0: Sysopt=0: Configuration Port Address 0x00 0x00 Byte 1 Sysopt=1: Sysopt=1: (High Byte) 0x00 0x00 Reserved 0x00 0x00 TEST 6 0x00 0x00 TEST 4 0x00 0x00 TEST 5 0x00 0x00 TEST 1 0x00 0x00 TEST 2 0x00 0x00 TEST 3 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) 0x00 0x00 0x00 0x00 Activate 0x03, 0x03, 0x03, 0x03, Primary Base I/O Address 0xF0 0xF0 0xF0 0xF0 0x06 0x06 0x06 0x06 Primary Interrupt Select 0x02 0x02 0x02 0x02 DMA Channel Select 0x0E 0x0E 0x0E FDD Mode Register 0x00 0x00 0x00 FDD Option Register 0xFF 0xFF 0xFF FDD Type Register 0x00 0x00 0x00 FDD0 0x00 0x00 0x00 FDD1 LOGICAL DEVICE 1 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x00 0x00 0x00 0x00 Activate 0x00, 0x00, 0x00, 0x00, Primary Base I/O Address 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Primary Interrupt Select 0x04 0x04 0x04 0x04 DMA Channel Select 0x3C 0x3C 0x3C Parallel Port Mode Register 0x00 0x00 0x00 Parallel Port Mode Register 2 LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) 0x00 0x00 0x00 0x00 Activate 0x00, 0x00, 0x00, 0x00, Primary Base I/O Address 0x00 0x00 0x00 0x00 PCI RESET VCC POR VTR POR Vbat POR
Page 196 of 259 Rev. 04-30-07
0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26
W R R/W R R R/W R/W R/W R/W
0x27 0x28 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF5
R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0x30 0x60, 0x61
R/W R/W R/W R/W R/W R/W R/W R/W
SMSC LPC47S45x
DATASHEET
INDEX
TYPE
0x70 0xF0 0x30 0x60, 0x61 0x70 0xF0 0xF1 0xF2 0x30 0x60, 0x61 0x62, 0x63 0x70 0xF0 00xF1 0x30 0x70 0x72 0xF0 0x30 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0xF0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W (Note1) R/W (Note1) R/W (Note1) R/W (Note1) R/W (Note1) R/W (Note1) R/W
PCI SOFT CONFIGURATION VCC POR VTR POR Vbat POR RESET RESET REGISTER 0x00 0x00 0x00 0x00 Primary Interrupt Select 0x00 0x00 0x00 Serial Port 1 Mode Register LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2) 0x00 0x00 0x00 0x00 Activate 0x00, 0x00, 0x00, 0x00, Primary Base I/O Address 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Primary Interrupt Select 0x00 0x00 0x00 Serial Port 2 Mode Register 0x02 0x02 0x02 IR Options Register 0x03 0x03 0x03 IR Half Duplex Timeout LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RTC) 0x00 0x00 0x00 0x00 Activate 0x00, 0x00, 0x00, 0x00, RTC Bank 0 Primary Base Address 0x70 0x70 0x00 0x70
0x00, 0x74 0x00
Primary Interrupt Select Real Time Clock Mode 0x00 0x00 0x00 Register Shadowed RTC/CMOS Bank 0 Index Register LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard) 0x00 0x00 0x00 0x00 Activate Primary Interrupt Select 0x00 0x00 0x00 0x00 (Keyboard) Secondary Interrupt Select 0x00 0x00 0x00 0x00 (Mouse) 0x00 0x00 0x00 KRESET and GateA20 Select LOGICAL DEVICE 8 CONFIGURATION REGISTERS (X-Bus) 0x00 0x00 0x00 0x00 Activate Base I/O Address 0 - High 0x00 0x00 0x00 0x00 Byte Base I/O Address 0 - Low 0x00 0x00 0x00 0x00 Byte Base I/O Address 1 - High 0x00 0x00 0x00 0x00 Byte 0x00 Base I/O Address 1 - Low 0x00 0x00 0x00 Byte (Note 2) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (Note 2) 0x00 Base I/O Address 2 - High Byte Base I/O Address 2 - Low Byte Base I/O Address 3 - High Byte
0x00, 0x74 0x00
0x00, 0x00 0x00
-
0x00, 0x74 0x00
RTC Bank 1 Primary Base Address
0x30 0x60,
R/W R/W
0x00 Base I/O Address 3 - Low Byte (Note 2) (Note 3) (Note 3) 0x0C X-Bus Selection LOGICAL DEVICE 9 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE A CONFIGURATION REGISTERS (Runtime Registers) 0x00 0x00 0x00 0x00 Activate 0x00, 0x00, 0x00, 0x00, Primary Base I/O Address
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INDEX
TYPE
0x61 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0XF0 0XF1 0xF4 0xF5 0xF6 0xF8 0x30 0x60, 0x61 0x70 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PCI RESET 0x00 -
VCC POR
VTR POR
Vbat POR
GP70 GP71 GP72 GP73 GP74 GP75 GP76 GP77 GP80 GP81 GP82 GP83 GP84 GP85 GP85 GP87 Clock Select Register IRQ8 Polarity IRQIN Routing Register 1 IRQIN Routing Register 2 Power-On-Reset Select 0x00 Register for GP8 Power Supply Control 0x00 Register LOGICAL DEVICE B CONFIGURATION REGISTERS (SMBus) 0x00 0x00 0x00 0x00 Activate SMBus Primary Base I/O 0x00, 0x00, 0x00, 0x00, Address Runtime Register 0x00 0x00 0x00 0x00 Block 0x00 0x00 0x00 0x00 Primary Interrupt Select
0x00 -
0x00 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x00 0x00 0x00 0x00
-
SOFT RESET 0x00 -
CONFIGURATION REGISTER Runtime Register Block
Note: Reserved registers are read-only, reads return 0. Note 1: These registers are read-only if the write protect bit is set in the associated base I/O address low byte register. Note 2: Bit 1 is reset on VCC POR, VTR POR and PCI RESET only. Note 3: Bit 7 is reset on VCC POR, VTR POR and PCI RESET.
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9.4
Chip Level (Global) Control/Configuration Registers[0x00-0x2F]
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode.
Table 82 - Chip Level Registers REGISTER ADDRESS (Type) DESCRIPTION Chip (Global) Control Registers Reserved - Writes are ignored, reads return 0. STATE
Config Control Default = 0x00 on VCC POR , VTR POR and PCI RESET N/A Logical Device # Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET Card Level Reserved Device ID Default = 0x62 VCC POR, VTR POR, PCI RESET and SOFT RESET Device Rev Default = Current Rev VCC POR, VTR POR, PCI RESET and SOFT RESET
0x00 0x01 0x02 (W)
The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit 0 = 1: Soft Reset. Refer to the "Configuration Registers" table for the soft reset value for each register.
C
0x03 - 0x06 0x07 (R/W)
Reserved - Writes are ignored, reads return 0. A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: The Activate command operates only on the selected logical device. C
0x08 - 0x1F 0x20 (R)
Reserved - Writes are ignored, reads return 0. Chip Level, SMSC Defined A read only register which provides device identification. C Bits[7:0] = 0x62 when read.
0x21 (R)
A read only information..
register
which
provides
device
revision C
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Table 82 - Chip Level Registers REGISTER ADDRESS (Type) 0x22 DESCRIPTION STATE
PowerControl Default = 0x00. on VCC POR, VTR POR, PCI RESET and SOFT RESET
(R/W)
Power Mgmt Default = 0x00. on VCC POR, VTR POR and PCI RESET
0x23 (R/W)
Bit[0] FDC Power Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power Bit[5] Serial Port 2 Power Bit[6] Reserved Bit[7] Reserved 0: Power Off or Disabled 1: Power On or Enabled Bit[0] FDC (see Note in the "FDC Power Management" section.) Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Bit[4] Serial Port 1 Bit[5] Serial Port 2 Bit[7:6] Reserved (read as 0) For each bit above (except Reserved) =0 Intelligent Pwr Mgmt off =1 Intelligent Pwr Mgmt on Bit[0] Reserved Bit [1] PLL Control =0 PLL is on (backward Compatible) =1 PLL is off Bits[3:2] OSC = 01 Osc is on, BRG clock is on. = 10 Same as above (01) case. = 00 Osc is on, BRG Clock Enabled. = 11 Osc is off, BRG clock is disabled. Bit [5:4] Reserved, set to zero Bit [6] 16-Bit Address Qualification =0 12-Bit Address Qualification =1 16-Bit Address Qualification Note: For normal operation, bit 6 should be set. Bit[7] Reserved Reserved - Writes are ignored, reads return 0. Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0 (See Note 1)
C
C
OSC Default = 0x04 on VCC POR , VTR POR and PCI RESET
0x24 (R/W)
C
Chip Level Vendor Defined Configuration Port Address Byte 0 (Low Byte) Default =0x2E (Sysopt=0) =0x4E (Sysopt=1) on VCC POR and PCI RESET
0x25 0x26 (R/W)
C
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Table 82 - Chip Level Registers REGISTER ADDRESS (Type) 0x27 DESCRIPTION STATE
Configuration Port Address Byte 1 (High Byte)
Bit[7:0] Configuration Address Bits [15:8] (See Note 1)
C
(R/W)
Default = 0x00 on VCC POR and PCI RESET N/A Chip Level Vendor Defined TEST 6 Default = 0x00 on VCC POR and VTR POR TEST 4 Default = 0x00 on VCC POR and VTR POR TEST 5 Default = 0x00 on VCC POR and VTR POR
0x28 0x29 0x2A (R/W)
Bits[7:0] Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
0x2B (R/W)
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
C
0x2C (R/W)
TEST 1 Default = 0x00 on VCC POR and VTR POR TEST 2 Default = 0x00 on VCC POR and VTR POR TEST 3 Default = 0x00 on VCC POR and VTR POR
0x2D (R/W)
Bit[7] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Bit[6] 8042 Reset: 1 = put the 8042 into reset 0 = take the 8042 out of reset Bits[5:0] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
C
C
0x2E (R/W)
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
C
0x2F (R/W)
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
C
Note 1: To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address).
The configuration address is only reset to its default address upon a PCI Reset or VCC POR.
Note: The default configuration address is either 0x02E or 0x04E, as specified by the SYSOPT pin.
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9.5
Logical Device Configuration/Control Registers [0x30-0xFF]
Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The nine logical devices are Floppy, Parallel, Serial 1, Serial 2, Real Time Clock (RTC), Keyboard Controller, SMBus Controller, X-Bus and Runtime Registers. A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in the table below.
Table 83 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS (0x30) DESCRIPTION Bits[7:1] Reserved, set to zero. Bit[0] =1 Activates the logical device currently selected through the Logical Device # register. =0 Logical device currently selected is inactive STATE C
Activate (Note 1) Default = 0x00 on VCC POR , VTR POR, PCI RESET and SOFT RESET Logical Device Control Logical Device Control Memory Base Address I/O Base Address (Note 2) (see Device Base I/O Address Table) Default = 0x00 (Note 5) on VCC POR, VTR POR, PCI RESET and SOFT RESET Interrupt Select Defaults : 0x70 = 0x00 or 0x06 (Note 3) on VCC POR, VTR POR, PCI RESET and SOFT RESET 0x72 = 0x00, on VCC POR, VTR POR, PCI RESET and SOFT RESET
(0x31-0x37) (0x38-0x3f) (0x40-0x5F) (0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0]
Reserved - Writes are ignored, reads return 0. Vendor Defined - Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 84 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read. See the FDD, RTC, X-Bus and SMBus Logical Device Configuration registers for a description of their respective Base I/O registers. 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible).
C C C C
(0x70,0x72)
C
(0x71,0x73)
Reserved - not implemented. These register locations ignore writes and return zero when read.
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Table 83 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS (0x74,0x75) DESCRIPTION Only 0x74 is implemented for FDC and Parallel port. 0x75 is not implemented and ignores writes and returns zero when read. Refer to DMA Channel Select Configuration register description. STATE C
DMA Channel Select Default = 0x02 or 0x04 (Note 4) on VCC POR, VTR POR, PCI RESET and SOFT RESET 32-Bit Memory Space Configuration Logical Device
Reserved - not implemented. These register locations ignore writes and return zero when read. (0xA9-0xDF) Reserved - not implemented. These register locations ignore writes and return zero when read. (0xE0-0xFE) Reserved - Vendor Defined (see SMSC defined Logical Device Logical Device Configuration Configuration Registers). Reserved 0xFF Reserved Note 1: A logical device will be active and powered up according to the following equation:
(0x76-0xA8)
C C C
Note 2: Note 3: Note 4: Note 5:
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. The default value of the Primary Interrupt Select register for logical device 0 is 0x06. The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is 0x04. The default values for the Primary Base I/O Address Register for logical device 0 (FDD) are 0x60=0x03 and 0x61=0xF0.
Table 84 - I/O Base Address Configuration Register Description
LOGICAL DEVICE NUMBER 0x00
LOGICAL DEVICE FDC
REGISTER INDEX
0x60,0x61
BASE I/O RANGE (Note 1) [0x0100:0x0FF8]
FIXED BASE OFFSETS
on 8-byte boundaries
0x01 0x02 0x03
Reserved Reserved Parallel Port
n/a n/a 0x60,0x61
n/a n/a [0x0100:0x0FFC] on 4-byte boundaries (EPP Not supported) or [0x0100:0x0FF8] on 8-byte boundaries (all modes supported, EPP is only available when the base address is on an 8-byte boundary)
+0 : SRA +1 : SRB +2 : DOR +3 : TDR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR n/a n/a +0 : Data/ecpAfifo +1 : Status +2 : Control +400h : cfifo/ecpDfifo/tfifo/cnfgA +401h : cnfgB +402h : ecr +3 : EPP Address +4 : EPP Data 0 +5 : EPP Data 1 +6 : EPP Data 2 +7 : EPP Data 3
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Table 84 - I/O Base Address Configuration Register Description LOGICAL DEVICE NUMBER 0x04 LOGICAL DEVICE Serial Port 1 REGISTER INDEX BASE I/O RANGE (Note 1) [0x0100:0x0FF8] FIXED BASE OFFSETS +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR Bank 0 Base address +0 : Address Register +1 : Data Register Bank 1 Base address +0 : Address Register +1 : Data Register +0 : Data Register +4 : Command/Status Reg.
0x60,0x61
on 8 byte boundaries
0x05
Serial Port 2
0x60,0x61
[0x0100:0x0FF8] on 8-byte boundaries
0x06
RTC
0x60, 0x61 0x62, 0x63
[0x100:0x0FFE]
[0x100:0x0FFD]
0x07
KYBD
n/a
Not Relocatable Fixed Base Address: 60,64
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Table 84 - I/O Base Address Configuration Register Description LOGICAL DEVICE NUMBER 0x08 LOGICAL DEVICE X-Bus REGISTER INDEX BASE I/O RANGE (Note 1) Mode 1 and Mode 2: [0x0000:0x0FFF] ON 1 BYTE BOUNDARIES Mode 1 and Mode 2: [0x0000:0x0FFC] ON 4 BYTE BOUNDARIES Mode 1: [0x0000:0x0FFC] ON 4 BYTE BOUNDARIES Mode 2: [0x0000:0x0FF0] ON 16 BYTE BOUNDARIES Mode 1: [0x0000:0x0FFC] ON 4 BYTE BOUNDARIES Mode 2: [0x0000:0x0FF0] ON 16 BYTE BOUNDARIES n/a [0x0000:0x0F80] on 128-byte boundaries FIXED BASE OFFSETS +0: X-BUS CS0 ADDRESS
0x60,0x61
0x62,0x63
+0: X-BUS CS1 ADDRESS
0x64,0x65
+0: X-BUS CS2 ADDRESS
0x66,0x67
+0: X-BUS CS3 ADDRESS
n/a +00 : PME_STS . . . (See Table in "Runtime Registers" section for Full List) 0x0B SMBus 0x60, 0x61 [0x0100:0x0FF8] +0: Control/Data on 8-byte boundaries +1: Own Address +2: Data +3: Clock Config. Port 0x26, 0x27 0x0100:0x0FFE See Configuration Registers in Config. Port (Note 2) On 2-byte boundaries Table 85. Accessed through the index and DATA ports located at the Configuration Port address and the Configuration Port address +1 respectively. Note 1: This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to `1' and Address Bits [A15:A12] must be `0' for 16 bit address qualification.
Note 2: The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power up and can be relocated via the global configuration registers at 0x26 and 0x27.
0x09 0x0A
Reserved Runtime Register Block
n/a 0x60,0x61
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Table 85 - Interrupt Select Configuration Register Description NAME Primary Interrupt Select REG INDEX 0x70 DEFINITION Bits[3:0] selects which interrupt level is used for the primary Interrupt. 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2/nSMI 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 0x06= IRQ6 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Note: All interrupts are edge high (except ECP/EPP) Note: nSMI is active low Note: The polarity of IRQ8 is programmable via bit 0 of register 0xF1 in Logical Device A. STATE C
(R/W) Default=0x00 or 0x06 (Note 1) on VCC POR, VTR POR, PCI RESET and SOFT RESET
Bits[7:4] Reserved
Note:
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND:
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. For the KYBD logical device (refer to the KYBD controller section of this spec). For the SMBus logical device by setting ENI, bit D3 of the Control Register.
Note: Note: Note: Note 1:
IRQs are disabled if not used/selected by any Logical Device. Refer to Note A. nSMI must be disabled to use IRQ2. All IRQ's are available in Serial IRQ mode. The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Table 86 - DMA Channel Select Configuration Register Description NAME DMA Channel Select REG INDEX 0x74 (R/W) DEFINITION Bits[2:0] select the DMA Channel. 0x00= Reserved 0x01= DMA1 0x02= DMA2 0x03= DMA3 0x04-0x07= No DMA active STATE C
Default=0x02 or 0x04 (Note 1) on VCC POR, VTR POR, PCI RESET and SOFT RESET
Note:
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
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Note: DMA channels are disabled if not used/selected by any Logical Device. Refer to Note A. Note 1: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device 3 is 0x04.
Note A. Logical Device IRQ and DMA Operation
1.
IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is disabled by a register bit in that logical block, the IRQ and/or DMA channel must be disabled. This is in addition to the IRQ and DMA channel disabled by the Configuration Registers (active bit or address not valid). FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled. Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". The FDC is in power down (disabled). Serial Ports: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is disabled. Parallel Port: I. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled. ii. ECP Mode: (1) (DMA) dmaEn from ecr register. See table below. (2) IRQ - See table below.
MODE (FROM ECR REGISTER) 000 PRINTER 001 SPP 010 FIFO 011 ECP 100 EPP 101 RES 110 TEST 111 CONFIG IRQ DMA CONTROLLED BY CONTROLLED BY IRQE dmaEn IRQE dmaEn (on) dmaEn (on) dmaEn IRQE dmaEn IRQE dmaEn (on) dmaEn IRQE dmaEn
a)
b) c)
d) e)
Keyboard Controller: Refer to the KBD section of this spec. SMBus Controller: Control Register Bit D3 (ENI) - When ENI is a logic "0" the SMBus interrupt is disabled.
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SMSC Defined Logical Device Configuration Registers
The SMSC Specific Logical Device Configuration Registers (0xE0-0xFE) reset to their default values only on VCC POR, VTR POR , or PCI RESET signal as shown. These registers are not affected by soft resets.
Table 87 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME Primary Base I/O Address (High Byte) REG INDEX 0x60 DEFINITION Registers 0x60 and 0x61 set the base address for the device. STATE C
Default = 0x03 on VCC POR, VTR POR, PCI RESET and SOFT RESET
Refer to Table 84 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read. If the I/O Base Address of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored.
Primary Base I/O Address (Low Byte) Default = 0xF0 on VCC POR, VTR POR, PCI RESET and SOFT RESET FDD Mode Register Default = 0x0E on VCC POR , VTR POR and PCI RESET
0x61
Registers 0x60 and 0x61 set the base address for the device. Refer to Table 84 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read. If the I/O Base Address of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored.
C
0xF0 (R/W)
Bit[0] Floppy Mode =0 Normal Floppy Mode (default) =1 Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode =0 Burst Mode is enabled =1 Non-Burst Mode (default) Bit[3:2] Interface Mode = 11 AT Mode (default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit[4] Reserved Bit[5] Reserved, set to zero Bit[6] FDC Output Type Control =0 FDC outputs are OD12 open drain (default) =1 FDC outputs are O12 push-pull Bit[7] FDC Output Control =0 FDC outputs active (default) =1 FDC outputs tri-stated
C
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Table 87 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME FDD Option Register REG INDEX 0xF1 DEFINITION Bit[0] Forced Write Protect = 0 Inactive (default) = 1 FDD nWRTPRT input is forced active when either of the drives has been selected. Bit[1] Reserved Bits[3:2] Density Select = 00 Normal (default) = 01 Normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") Bit[7:4] Reserved. nWRTPRT (to the FDC Core) = WP (FDC SRA Register, Bit 1) = (Floppy Write Protect) OR nWRTPRT(from the FDD Interface) OR (nDS0 AND Force Write Protect ) OR (nDS1 AND Force Write Protect ). Note: Floppy Write Protect bit is in the Device Disable register. Note: Boot floppy is always drive 0. Note: the Force Write Protect bits also apply to the Parallel Port FDC. Bits[1:0] Floppy Drive A Type Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The LPC47S45x supports two floppy drives STATE C
Default = 0x00 on VCC POR, VTR POR and PCI RESET
(R/W)
FDD Type Register Default = 0xFF on VCC POR, VTR POR and PCI RESET
0xF2 (R/W)
C
FDD0 Default = 0x00 on VCC POR, VTR POR and PCI RESET
0xF3 (R) 0xF4 (R/W)
Reserved, Read as 0 (read only) Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] Read as 0 (read only) Bits[6] Precompensation Disable PTS =0 Use Precompensation =1 No Precompensation Bits[7] Read as 0 (read only) Refer to definition and default for 0xF4
C C
FDD1
0xF5 (R/W)
C
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Table 88 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME PP Mode Register REG INDEX 0xF0 DEFINITION Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-directional (SPP) Mode = 001 EPP-1.9 and SPP Mode = 101 EPP-1.7 and SPP Mode = 010 ECP Mode = 011 ECP and EPP-1.9 Mode = 111 ECP and EPP-1.7 Mode STATE C
Default = 0x3C on VCC POR , VTR POR and PCI RESET
(R/W)
Bit[6:3] ECP FIFO Threshold 0111b (default) Bit[7] PP Interupt Type Not valid when the parallel port is in the Printer Mode (100) or the Standard & Bi-directional Mode (000). =1 Pulsed Low, released to high-Z. =0 IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode. Bits[1:0] PPFDC - muxed PP/FDC control = 00 Normal Parallel Port Mode = 01 PPFD1: Drive 0 is on the FDC pins Drive 1 is on the Parallel port pins = 10 PPFD2: Drive 0 is on the Parallel port pins Drive 1 is on the Parallel port pins Bits[7:2] Reserved. Set to zero.
PP Mode Register 2 Default = 0x00 on VCC POR, VTR POR and PCI RESET
0xF1 (R/W)
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Table 89 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX DEFINITION STATE
Serial Port 1 Mode Register Default = 0x00 on VCC POR , VTR POR and PCI RESET
0xF0 (R/W)
Bit[0] MIDI Mode =0 MIDI support disabled (default) =1 MIDI support enabled Bit[1] High Speed =0 High Speed Disabled(default) =1 High Speed Enabled Bit[6:2] Reserved, set to zero Bit[7]: Share IRQ =0 UARTS use different IRQs =1 UARTS share a common IRQ See Note 1 below.
C
Note 1: To properly share and IRQ, 1. Configure UART1 (or UART2) to use the desired IRQ pin. 2. Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. Note: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt. UART Interrupt Operation Table Table 90 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME Serial Port 2 Mode Register REG INDEX 0xF0 R/W DEFINITION
Default = 0x00 on VCC POR, VTR POR and PCI RESET
Bit[0] MIDI Mode =0 MIDI support disabled (default) =1 MIDI support enabled Bit[1] High Speed =0 High Speed disabled(default) =1 High Speed enabled Bit[7:2] Reserved, set to zero
STATE C
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Table 90 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME IR Option Register REG INDEX 0xF1 DEFINITION Bit[0] Receive Polarity =0 Active High (Default) =1 Active Low Bit[1] Transmit Polarity =0 Active High =1 Active Low (Default) Bit[2] Duplex Select =0 Full Duplex (Default) =1 Half Duplex STATE C
Default = 0x02 On VCC POR, VTR POR and PCI RESET
(R/W)
Bits[5:3] IR Mode = 000 Standard COM Functionality (Default) = 001 IrDA = 010 ASK-IR = 011 Reserved = 1xx Reserved Bit[6] Reserved, write 0. Bit[7] Reserved, write 0. Bits [7:0] These bits set the half duplex time-out for the IR port. This value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec
IR Half Duplex Timeout Default = 0x03 on VCC POR, VTR POR and PCI RESET
0xF2 (R/W)
Table 91 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME
Activate Default = 0x00 on VCC POR, VTR POR, PCI RESET, and Soft Reset RTC/CMOS Bank 0 Primary Base Address (High Byte) Default = 0x00 on VCC POR, VTR POR, PCI RESET, and Soft Reset RTC/CMOS Bank 0 Primary Base Address (Low Byte) Default = 0x70 on VCC POR, PCI RESET, and Soft Reset Default = 0x00 on VTR_POR
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REG INDEX 0x30
R/W
Bit [0] Bit [1] Bits [7:2]
DEFINITION Activate RTC/CMOS Bank 0 Activate CMOS Bank 1 Reserved
STATE
0x60 R/W
Bits [3:0] Address bits A[11:8] Bits [7:4] "0000"
0x61 R/W
Bit [0] "0" Bits [7:1] Address bits A[7:1]
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Table 91 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME CMOS Bank 1 Primary Base Address (High Byte) REG INDEX 0x62 DEFINITION Bits [3:0] Address bits A[11:8] Bits [7:4] "0000" STATE
R/W
Default = 0x00 on VCC POR, VTR POR, PCI RESET, and Soft Reset CMOS Bank 1 Primary Base Address (Low Byte) Default = 0x74 on VCC POR, PCI RESET, and Soft Reset Default = 0x00 on VTR_POR Bank 1 Default = 0x00 on VCC POR, VTR POR, and PCI RESET
0x63 R/W
Bit [0] "0" Bits [7:1] Address bits A[7:1]
0xF0 R/W
Bank 0 Shadow Register
0xF1 Read-Only
Bank 1: Bit[0] = 1 : Lock CMOS RAM 0-1Fh Bit[1] = 1 : Lock CMOS RAM 20-3Fh Bit[2] = 1 : Lock CMOS RAM 40-5Fh Bit[3] = 1 : Lock CMOS RAM 60-7Fh Bit[7:4] Reserved, set to "0" Once set, bit[3:0] can not be cleared by a write; bits[3:0] are cleared on VCC Power On Reset, VCC Power Off, or upon a PCI Reset. Once lock bits are set, the Host is locked out of accessing the locked locations as long as VCC is active. When VCC goes to 0V, the lock bits are cleared. Shadow of RTC/CMOS Bank 0 Index register
Table 92 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME KRST_GA20 REG INDEX 0xF0 R/W DEFINITION KRESET and GateA20 Select Bit[7] Polarity Select for P12 = 0 P12 active low (default) = 1 P12 active high Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect MDAT signal to mouse wakeup (PME) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect KDAT signal to keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 Bit[4] MLATCH = 0 MINT is the 8042 MINT ANDed with Latched MINT (default)
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STATE
Default = 0x00 on VCC POR, VTR POR and PCI RESET Bits[6:5] reset on VTR POR only
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Table 91 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME REG INDEX DEFINITION = 1 MINT is the latched 8042 MINT Bit[3] KLATCH = 0 KINT is the 8042 KINT ANDed with Latched KINT (default) = 1 KINT is the latched 8042 KINT Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] Reserved Bit[0] Reserved Reserved - read as `0' STATE
0xF1 0xFF
Table 93 - X-Bus, Logical Device 8 [Logical Device Number = 0x08] NAME Base I/O Address 0 - High Byte (Note 1) REG INDEX 0x60 DEFINITION Register 0x60 sets the high byte of the base I/O address for chip select 0. STATE
R/W Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset Base I/O Address 0 - Low Byte (Note 1) Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset Base I/O Address 1 - High Byte (Note 1) Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset 0x61 R/W Bits[7:0] = Address[7:0] Bits [7:0] =Address[15:8] Note: Bits[15:12] must be `0' since the chip performs 16-bit address qualification on the base I/O addresses. Register 0x61 sets the low byte of the base I/O address for chip select 0.
0x62 R/W, Read-Only when the Base I/O Address 1 - Low Byte Register bit[1]=1
Register 0x62 sets the high byte of the base I/O address for chip select 1. Bits [7:0] =address[15:8]
Note: Bits[15:12] must be `0' since the chip performs 16-bit address qualification on the base I/O addresses.
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Table 93 - X-Bus, Logical Device 8 [Logical Device Number = 0x08] NAME Base I/O Address 1 - Low Byte (Note 1) REG INDEX 0x63 DEFINITION Register 0x63 sets the low byte of the base I/O address for chip select 1. Bit 1 is the write protect bit for registers 62 and 63. Bit 0 is the disable bit for XCS1. STATE
Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset Bit 1 is reset on VCC POR, VTR POR and PCI Reset
R/W, Read-Only when the Base I/O Address 1 - Low Byte Register bit[1]=1
Bits [7:2] =address[7:2] Bit[1] = Register 62, 63 Write Protect. Cleared by VCC POR, VTR POR and PCI Reset only. Cannot be cleared by software writing to this bit. 0=Register 62 and 63 are read/write 1=Register 62 and 63 are read-only Bit[0] = Disable bit for XCS1. 0=enable chip select 1=disable chip select Register 0x64 sets the high byte of the base I/O address for chip select 2. Bits [7:0] =address[15:8]
Note: Bits[15:12] must be `0' since the chip performs 16-bit address qualification on the base I/O addresses.
Base I/O Address 2 - High Byte (Note 1) Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset Base I/O Address 2 - Low Byte (Note 1) Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset Bit 1 is reset on VCC POR, VTR POR and PCI Reset
0x64 R/W, Read-Only when the Base I/O Address 2 - Low Byte Register bit[1]=1 0x65 R/W, Read-Only when the Base I/O Address 2 - Low Byte Register bit[1]=1
Register 0x65 sets the low byte of the base I/O address for chip select 2. Bit 1 is the write protect bit for registers 64 and 65. Bit 0 is the disable bit for nXCS2. Mode 1: Bits [7:2] =address[7:2] Mode 2: Bits [7:4] =address[7:4] Bits [3:2] are reserved Bit[1] = Register 64, 65 Write Protect. Cleared by VCC POR, VTR POR and PCI Reset only. Cannot be cleared by software writing to this bit. 0=Register 64 and 65 are read/write 1=Register 64 and 65 are read-only Bit[0] = Disable bit for nXCS2. 0=enable chip select 1=disable chip select Register 0x66 sets the high byte of the base I/O address for chip select 3. Bits [7:0] =address[15:8]
Note: Bits[15:12] must be `0' since the chip performs 16-bit address qualification on the base I/O addresses.
Base I/O Address 3 - High Byte (Note 1) Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset
0x66 R/W, Read-Only when the Base I/O Address 3 - Low Byte Register bit[1]=1
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Table 93 - X-Bus, Logical Device 8 [Logical Device Number = 0x08] NAME Base I/O Address 3 - Low Byte (Note 1) REG INDEX 0x67 DEFINITION Register 0x67 sets the low byte of the base I/O address for chip select 3. Bit 1 is the write protect bit for registers 66 and 67. Bit 0 is the disable bit for nXCS3. STATE
Default = 0x00 on VTR POR, VCC POR, PCI Reset and Soft Reset Bit 1 is reset on VCC POR, VTR POR and PCI Reset
R/W, Read-Only when the Base I/O Address 3 - Low Byte Register bit[1]=1
Mode 1: Bits [7:2] =address[7:2] Mode 2: Bits [7:4] =address[7:4] Bits [3:2] are reserved Bit[1] = Register 66, 67 Write Protect. Cleared by VCC POR, VTR POR, and PCI Reset only. Cannot be cleared by software writing to this bit. 0=Register 66 and 67 are read/write 1=Register 66 and 67 are read-only
Bit[0] = Disable bit for nXCS3. 0=enable chip select 1=disable chip select Bit[0] X-Bus Mode. X-Bus Selection 0xF0 0=Mode 1 1=Mode 2 (R/W) Default = 0x0C on VTR POR Note that the GPIOs must be configured properly to use the selected mode. The GPIOs are not automatically configured for the mode selected. Bit 7 is reset on Bit[1] Reserved VCC POR, VTR POR Bits[3:2] X-Bus Read/Write Pulse Width Selection. These bits and PCI Reset select the pulse width of the X-bus read and write strobes. They extend the LPC cycle accordingly by adding wait states (sync fields) into the cycle. 11=540nsec min (default) 10=420nsec min 01=300nsec min 00=180nsec min Bits[6:4] Reserved Bit[7] Register Write Protect. Cleared by VCC POR, VTR POR and PCI Reset only. Cannot be cleared by software writing this bit. 0=X-Bus selection register is Read/Write. 1=X-Bus Selection register is Read-Only Note 1: If the I/O Base Address of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored.
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Table 94 - Runtime Registers, Logical Device A NAME
GP70 Default = 0x04 on VTR POR
GP71 Default = 0x04 on VTR POR
GP72 Default = 0x04 on VTR POR
GP73 Default = 0x04 on VTR POR
GP74 Default = 0x04 on VTR POR
REG INDEX DEFINITION E0h General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nXWR (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 E1h Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Alternate Function Select 1= nXRD (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 E2h Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Alternate Function Select 1= XA0 (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull E3h General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= XA1 (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 E4h Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Alternate Function Select 1= XA2 (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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STATE
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Table 94 - Runtime Registers, Logical Device A NAME
GP75 Default = 0x04 on VTR POR
GP76 Default = 0x04 on VTR POR
GP77 Default = 0x04 on VTR POR
GP80 Default = 0x80 on VTR POR
GP81 Default = 0x80 on VTR POR
REG INDEX DEFINITION E5h General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= XA3 (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 E6h Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Alternate Function Select 1= nXCS0 (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 E7h Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Alternate Function Select 1= XCS1 (default) 0= GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull E8h General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull E9h General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
STATE
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Table 94 - Runtime Registers, Logical Device A NAME
GP82 Default = 0x80 on VTR POR
GP83 Default = 0x80 on VTR POR
GP84 Default = 0x80 on VTR POR
GP85 Default = 0x80 on VTR POR
GP86 Default = 0x80 on VTR POR
GP87 Default = 0x80 on VTR POR
REG INDEX DEFINITION EAh General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull EBh General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull ECh General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 EDh Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 EEh Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.4 EFh Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert (R/W) Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
STATE
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Table 94 - Runtime Registers, Logical Device A NAME Clock Select REG INDEX DEFINITION 0xF0 Bit[0] (CLK32_PRSN) See Note. 0 = Either a single-input 32kHz clock is connected to the CLKI32 pin or a crystal oscillator is connected to the XTAL1and XTAL2 pins (R/W) (crystal oscillator is default case). 1 = Neither the 32kHz clock nor the crystal oscillator are connected to the CLKI32 pin Note: When Bit[1]=1, the 32kHz clock is derived internally from the 14MHz clock input (see Note) STATE C
Default = 0x00 on VTR POR
Bit[1] SPEKEY_EN. This bit is used to turn the logic for the "wake on specific key" feature on and off. It will disable the 32kHz clock input to the logic when turned off. The logic will draw no power when disabled. 0= "Wake on specific key" logic is on (default) 1= "Wake on specific key" logic is off Bit[2] (CLKO40_PWR) 0 = 40MHz clock output is on (default) 1 = 40MHz clock output is off Bits[7:3] are reserved Bits[7:1] Reserved Bit[0] IRQ8 Polarity 0 = IRQ8 is active high (non-inverted). Default. 1 = IRQ8 is active low (inverted). Bits[7:4] IRQINB routing. Selects which serial interrupt is used for IRQINB. See bit mapping below. Bits[3:0] IRQINA routing. Selects which serial interrupt is used for IRQINA. See bit mapping below. Bits[7:4] and bits[3:0] mapping: 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2/nIO_SMI 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 0x06= IRQ6 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Note: nIO_SMI must be disabled to use IRQ2 for an interrupt other than SMI.
IRQ8 Polarity Default = 0x00 on VTR POR IRQIN Routing Register 1 Default = 0x00 on VTR POR
0xF1 (R/W) 0xF4 (R/W)
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Table 94 - Runtime Registers, Logical Device A NAME IRQIN Routing Register 2 REG INDEX DEFINITION 0xF5 Bits[7:4] IRQIND routing. Selects which serial interrupt is used for IRQIND. See bit mapping below. Bits[3:0] IRQINC routing. Selects which serial interrupt is used for (R/W) IRQINC. See bit mapping below. Bits[7:4] and bits[3:0] mapping: 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2/nIO_SMI 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 0x06= IRQ6 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Note: nIO_SMI must be disabled to use IRQ2 for an interrupt other than SMI. Power-on-Reset Selection register for GP8 F6h This register is used to select the reset conditions for each bit of the GP8 register and the corresponding GPIO configuration register (R/W) associated with that bit. The GP8 register is located in the Runtime Register block and the GP80 to GP87 registers are located in Logical Device A of the Configuration Block. STATE
Default = 0x00 on VTR POR
GP8_POR Select Default = 0x00 on VTR POR
Reset Select: 0=VTR POR 1=VTR POR, PCI Reset, and VCC POR Bit[0] Reset select for GP8 bit[0] and GP80 registers Bit[1] Reset select for GP8 bit[1] and GP81 registers Bit[2] Reset select for GP8 bit[2] and GP82 registers Bit[3] Reset select for GP8 bit[3] and GP83 registers Bit[4] Reset select for GP8 bit[4] and GP84 registers Bit[5] Reset select for GP8 bit[5] and GP85 registers Bit[6] Reset select for GP8 bit[6] and GP86 registers Bit[7] Reset select for GP8 bit[7] and GP87 registers Bit[0] AL_REM_EN If AL_REM_EN is set and VTR=0 at the date/time that the alarm is set for, then if the RTC_EN bit is set, the nPS_ON pin will go active (low) and the machine will power-up as soon as VTR comes back. This event is blocked when a power button override event occurs (PWRBTNOR_STS bit set). Bit[1] VTR_POR_OFF If VTR_POR_OFF is set, the nPS_ON pin will go inactive (float) and the main power (Vcc) will remain off when the VTR POR occurs. The software must not set VTR_POR_OFF and VTR_POR_EN at the
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Power Supply Control Register (PS_CNTRL) Default = 0x00 on Vbat POR
0xF8 (R/W)
DATASHEET
Table 94 - Runtime Registers, Logical Device A NAME REG INDEX DEFINITION same time. Note: if neither the VTR_POR_OFF bit nor the VTR_POR_EN bit is set then the system will return to the state it was in prior to the loss of VTR. STATE
Bit[2] VTR_POR_EN The enable bit for VTR POR. If VTR_POR_EN is set, the nPS_ON pin will go active (low) and the machine will power-up as soon as a VTR POR occurs. The software must not set VTR_POR_OFF and VTR_POR_EN at the same time. Note: if neither the VTR_POR_OFF bit nor the VTR_POR_EN bit is set then the system will return to the state it was in prior to the loss of VTR. This event is blocked when a power button override event occurs (PWRBTNOR_STS bit set). Bit[3] VTRPOR_STS This bit is set upon a VTR POR. This bit is only set by hardware and is reset by software writing a one to this bit position. Writing a 0 has no effect. No PME is generated when nPS_ON goes active due to VTR POR. Bit[4] WAK_CTRL 0= do not set the WAK STS Bit (PM1_STS2 register) 1= set the WAK_STS bit as described in PM1_STS2 register. Bit[5] SLP_CTRL 0=Writing a `1' to the SLP_EN bit (PM1_CNTRL2 register) causes the system to sequence into the sleeping state associated with the SLP_TYPx field 1= Writing a `1' to the SLP_EN bit does not sequence into the sleeping state associated with the SLP_TYPx field, but generates an SMI. Bit[6] SMI_SCI_ENB 0= generate an SMI for enabled SCI events when the SCI_EN bit is zero. Note: To generate an IO_SMI# signal, Bit[7] EN_SMI in the SMI_EN2 register at offset 17h in the Runtime Register block must be set to `1'. 1= do not generate an SMI for enabled SCI events when the SCI_EN bit is zero. Note: when the SCI_EN bit is one, there will never be an SMI event generated by the events in the PM1 or GPE1 registers. The GPE1 events can be enabled to generate an SMI separately through the SMI_ENx registers. Bit[7] PSOFF Writing this bit to `1' will force a software power down. Writing `0' has no effect. This bit is self-clearing. Note: XOSEL signal is used to differentiate between a 32kHz signal driven on the CLKI32 pin or an oscillator connected between XTAL1 and XTAL2. If a 32kHz signal is connected to the CLKI32 pin, the XOSEL pin should be pulled up to VTR. (A 10k pull-up resistor is suggested) If a crystal oscillator is connected across XTAL1 and XTAL2 or if no external clock is used then the XOSEL pin should be left unconnected. There is an internal pulldown on this pin that will keep this pin low when not in use. The XTAL2/CLKI32 pin is an output when the XOSEL pin is left unconnected and therefore, MUST NOT be grounded.
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Table 95 - SMBus [Logical Device Number = 0x0B] NAME SMBus Primary Base Address High Byte REG INDEX 0x60 R/W Bit[0] A8 Bit[1] A9 Bit[2] A10 Bit[3] A11 Bit[4] "0" Bit[5] "0" Bit[6] "0" Bit[7] "0" 0x61 R/W Bit[0] "0" Bit[1] "0" Bit[2] "0" Bit[3] A3 Bit[4] A4 Bit[5] A5 Bit[6] A6 Bit[7] A7 DEFINITION STATE C
Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET SMBus Primary Base Address Low Byte (Note 1)
C
Default = 0x00 on VTR POR, VCC POR, PCI RESET and SOFT RESET Note 1: The valid address range is 0x0100 - 0x0FF8.
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10 OPERATIONAL DESCRIPTION 10.1 Maximum Guaranteed Ratings
Operating Temperature Range........................................................................................................................... 0oC to +70oC Storage Temperature Range............................................................................................................................-55o to +150oC Lead Temperature Range ................................................................................................ Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground................................................................................................VCC+0.3V Negative Voltage on any pin, with respect to Ground .....................................................................................................-0.3V Maximum VCC..................................................................................................................................................................+5.5V
Note: Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
10.2 DC Electrical Characteristics
(TA = 00C - 700C, VCC = +3.3 V 10%) PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis Input Leakage, I and IS Buffers Low Input Leakage High Input Leakage
IO6 Type Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VILI VIHI 2.0
0.8
V V
TTL Levels
VILIS VIHIS VHYS 2.2 100
0.8
V V mV
Schmitt Trigger Schmitt Trigger
IIL IIH
-10 -10
+10 +10
A A
VIN = 0 VIN = VCC
Low Output Level High Output Level Leakage Current
OD6 Type Buffer
VOL VOH ILEAK 2.4
0.4
V V
IOL = 6mA IOH = -3mA VIN = 0 to VCC (Note 1)
10
A
Low Output Level Leakage Current
SMSC LPC47S45x
VOL ILEAK
Page 224 of 259
0.4 +10
V A
IOL = 6mA VIN = 0 to VCC
Rev. 04-30-07
DATASHEET
PARAMETER O6 Type Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Low Output Level High Output Level
IO8 Type Buffer
VOL VOH 2.4
0.4
V V
IOL = 6mA IOH = -3mA
Low Output Level High Output Level Leakage Current
OD8 Type Buffer
VOL VOH ILEAK 2.4
0.4
V V
IOL = 8mA IOH = -4mA VIN = 0 to VCC (Note 1)
10
A
Low Output Level Leakage Current O8 Type Buffer Low Output Level High Output Level
O12 Type Buffer
VOL ILEAK
0.4 +10
V A
IOL = 8mA VIN = 0 to VCC
VOL VOH 2.4
0.4
V V
IOL = 8mA IOH = -4mA
Low Output Level High Output Level
IO12 Type Buffer
VOL VOH 2.4
0.4
V V
IOL = 12mA IOH = -6mA
Low Output Level High Output Level Leakage Current
OD12 Type Buffer
VOL VOH ILEAK 2.4
0.4
V V
IOL = 12mA IOH = -6mA VIN = 0 to VCC (Note 1)
10
A
Low Output Level Leakage Current IOD12 Type Buffer Low Output Level Leakage Current
VOL ILEAK
0.4 +10
V A
IOL = 12mA VIN = 0 to VCC
VOL ILEAK
0.4
10
V A
IOL = 12mA VIN = 0 to VCC (Note 1)
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PARAMETER OD14 Type Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Low Output Level Leakage Current OP14 Type Buffer Low Output Level High Output Level IOP14 Type Buffer Low Output Level High Output Level Leakage Current
IOD16 Type Buffer
VOL ILEAK
0.4 +10
V A
IOL = 14mA VIN = 0 to VCC
VOL VOH 2.4
0.4
V V
IOL = 14mA IOH = -14mA
VOL VOH ILEAK 2.4
0.4
V V
IOL = 14mA IOH = -14mA VIN = 0 to VCC (Note 1)
10
A
Low Output Level Leakage Current
Backdrive Protect/ChiProtect (All pins excluding LAD[3:0], LDRQ#, LPCPD#, LFRAME#) 5V Tolerant Pins (All pins excluding LAD[3:0], LDRQ#, LPCPD#, LFRAME#) Inputs and Outputs in High Impedance State LPC Bus Pins (LAD[3:0], LDRQ#, LPCPD#, LFRAME#) VCC Supply Current Active
VOL ILEAK IIL
0.4
10
V A A
IOL = 16mA VIN = 0 to VCC (Note 1) VCC = 0V VIN = 5.5V Max
10
IIL
10
A
VCC = 3.3V VIN = 5.5V Max
IIL
10
A
ICC
203
mA
Trickle Supply Voltage
VTR
VCC min -.5V5
VCC max
V
VCC = 0V and VCC = 3.3V VIN = 3.6V Max All outputs open, all inputs at a known state (i.e., 0V or 3.3V). VCC must not be greater than .5V above VTR All outputs open, all inputs at a known state (i.e., 0V or 3.3V).
VTR Supply Current Active
IVTR
13,4
mA
Vbat for RTC
Vbat Supply Current Active
Vbat Ibat
2.4
3.0
3.3 2A
V mA All outputs open, all inputs at a known state (i.e., 0V or 3.3V).
Note 1: All output leakage's are measured with all pins in high impedance.
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DATASHEET
Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state. Note 3: These values are estimated. They will be updated after characterization. Contact SMSC for the latest values. Note 4: Max ITR with VCC = 3.3V (nominal) is 1mA. Max ITR with VCC = 0V (nominal) is 100A. Note 5: The minimum value give for VTR applies when VCC is active. When VCC is 0V, the minimum VTR is 0V. CAPACITANCE TA = 250C; fc = 1MHz; VCC = 3.3V 10% LIMITS TYP
PARAMETER Clock Input Capacitance
SYMBOL CIN
MIN
MAX 20
UNIT pF
TEST CONDITION All pins except pin under test tied to AC ground
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
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11 TIMING DIAGRAMS
For the Timing Diagrams shown, the following capacitive loads are used on outputs.
CAPACITANCE TOTAL (pF)
NAME SER_IRQ nLAD[3:0] nLDRQ nDIR nSTEP nDS0-1 nWDATA PD[0:7] nSTROBE nALF SLCTIN KDAT KCLK MDAT MCLK FAN LEDx TXD1 TXD2 SDAT SCLK nXCS[0:3] XA[0:3] XD[0:7] nXRD nXWR
50 50 50 240 240 240 240 240 240 240 240 240 240 240 240 50 50 50 50 50 50 50 50 50 50 50
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11.1 Power-Up Timing
t1 V cc
t2 t3
A ll H o s t A ccesses
FIGURE 13 - POWER-UP TIMING NAME DESCRIPTION MIN TYP MAX UNITS s s
t1 t2 t3
Vcc Slew from 2.7V to 0V Vcc Slew from 0V to 2.7V All Host Accesses After Powerup (Note 1)
300 100 125 500
s
Note 1: Internal write-protection period after Vcc passes 2.7 volts on power-up
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11.2 Input Clock Timing
t1
CLOCKI & CLKI32
t2
t2
FIGURE 14 - INPUT CLOCK TIMING NAME t1 t2 t1 DESCRIPTION Clock Cycle Time for 14.318MHZ Clock High Time/Low Time for 14.318MHz Clock Cycle Time for 32KHZ MIN TYP 69.84 35 31.25 MAX UNITS ns ns s s ns
20
t2
Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown)
16.53 5
11.3 Output Clock Timing
t1
CLKO40
t2
t2
FIGURE 15 - OUTPUT CLOCK TIMING
NAME t1
t2
DESCRIPTION Clock Cycle Time for 40.5340160MHZ Clock High Time/Low Time for 40.5340160MHz (60/40 or 40/60 duty cycle) Clock Rise Time/Fall Time (not shown) /10pF Load
MIN 24.69
TYP 24.63
MAX 24.57
UNITS ns
10 1.5
15
ns ns
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11.4 LPC Interface
t1 t5 t3
t4 t2
P C I_ C L K
FIGURE 16 - PCI CLOCK TIMING NAME t1 t2 t3 t4 t5 DESCRIPTION MIN 30 12 12 TYP MAX 33.3 UNITS nsec nsec nsec nsec nsec
Period High Time Low Time Rise Time Fall Time
3 3
PCI_RESET#
t4
FIGURE 17 - RESET TIMING NAME t4 DESCRIPTION PCI_RESET# width (Note 1) MIN 1 TYP MAX UNITS ms
Note 1: The PCI_RESET# width is dependent upon the PCI clock. The PCI_RESET# must be active low for a minumum of 100sec while the clock is running and stable and a minimum of 1ms after the system power good signal is asserted
CLK t1 Output Delay t2 t3 Tri-State Output
FIGURE 18 - OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME DESCRIPTION t1 CLK to Signal Valid Delay - Bused Signals t2 Float to Active Delay t3 Active to Float Delay MIN 2 2 TYP MAX 11 11 28 UNITS ns ns ns
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t1 CLK Input
Inputs Valid
t2
FIGURE 19 - INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME DESCRIPTION t1 Input Set Up Time to CLK - Bused Signals t2 Input Hold Time from CLK MIN 7 0 TYP MAX UNITS ns ns
PCI_CLK LFRAME# LAD[3:0]#
L1 L2 Address Data TAR Sync=0110 L3 TAR
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 FIGURE 20 - I/O WRITE
PCI_CLK LFRAME# LAD[3:0]#
L1 L2 Address TAR Sync=0110 L3 Data TAR
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 FIGURE 21 - I/O READ
PCI_CLK LDRQ#
Start MSB LSB ACT
FIGURE 22 - DMA REQUEST ASSERTION THROUGH LDRQ#
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PCI_CLK LFRAME# LAD[3:0]#
Start C+D CHL Size TAR Sync=0101 L1 Data TAR
Note: L1=Sync of 0000 FIGURE 23 - DMA WRITE (FIRST BYTE)
PCI_CLK LFRAME# LAD[3:0]#
Start C+D CHL Size Data TAR Sync=0101 L1 TAR
Note: L1=Sync of 0000 FIGURE 24 - DMA READ (FIRST BYTE)
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11.5 Floppy Disk Timing
nDIR t3
nSTEP t9 nDS0-1
t4 t1 t2
t5
nINDEX
t6
nRDAT
t7
nWDAT
t8
FIGURE 25 - FLOPPY DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP t4 nSTEP Cycle Time t5 nDS0-1 Hold Time from nSTEP Low (Note) t6 nINDEX Pulse Width t7 nRDATA Active Time Low t8 nWDATA Write Data Width Low t9 nDS0-1, Setup Time nDIR Low (Note) *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) Note: The nDS0-1 setup and hold times must be met by software. MIN TYP 4 24 96 132 20 2 40 .5 MAX UNITS X* X* X* X* X* X* ns Y* ns
0
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11.6 Parallel Port Timing
t1 nWRITE t3 PD<7:0> t4 t5 t6 nDATAST nADDRSTB t8 nWAIT
FIGURE 26 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION nWAIT Asserted to nWRITE Asserted (Note 1) nWAIT Asserted to nWRITE Change (Note 1) nWAIT Asserted to PDATA Invalid (Note 1) PDATA Valid to Command Asserted nWRITE to Command Asserted nWAIT Asserted to Command Asserted (Note 1) nWAIT Deasserted to Command Deasserted (Note 1) Command Asserted to nWAIT Deasserted MIN 60 60 0 10 5 60 60 TYP MAX 185 185 UNITS ns ns ns ns ns ns ns s ns
t2
t7
t9
35 210 190 10
t8 t9
0 0
Command Deasserted to nWAIT Asserted
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec.
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t1 nWRITE t3 PD<7:0> t7 t8 t9 DATASTB ADDRSTB t11 nWAIT
FIGURE 27 - EPP 1.9 DATA OR ADDRESS READ CYCLE DESCRIPTION MIN TYP MAX nWAIT Asserted to nWRITE Deasserted 0 185 nWAIT Deasserted to nWRITE Modified (Notes 1,2) 60 190 nWAIT Asserted to PDATA Hi-Z (Note 1) 60 180 Command Asserted to PDATA Valid 0 Command Deasserted to PDATA Hi-Z 0 nWAIT Deasserted to PDATA Driven (Note 1) 60 190 PDIR Set to Command 0 20 PDATA Hi-Z to Command Asserted 0 30 nWRITE Deasserted to Command 1 nWAIT Asserted to Command Asserted 0 195 nWAIT Deasserted to Command Deasserted 60 180 (Note 1) t12 PDATA Valid to nWAIT Deasserted 0 t13 PDATA Hi-Z to nWAIT Deasserted 0 Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. Note 2: When not executing a write cycle, EPP nWRITE is inactive high. NAME T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 t11
t2
t4
t5
t6
t10
t12
UNITS ns ns ns ns ns ns ns ns ns ns ns
ns s
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t1 nWRITE t2 PD<7:0> t3 t4 nDATASTB nADDRSTB t5 nWAIT
FIGURE 28 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE NAME t1 t2 t3 t4 t5 DESCRIPTION Command Deasserted to nWRITE Change Command Deasserted to PDATA Invalid PDATA Valid to Command Asserted nWRITE to Command Command Deasserted to nWAIT Deasserted MIN 0 50 10 5 0 TYP MAX 40 UNITS ns ns ns ns ns
35 35
nWRITE t1 PD<7:0> nDATASTB nADDRSTB t3 nWAIT
FIGURE 29 - EPP 1.7 DATA OR ADDRESS READ CYCLE NAME DESCRIPTION t1 Command Asserted to PDATA Valid t2 Command Deasserted to PDATA Hi-Z t3 Command Deasserted to nWAIT Deasserted MIN 0 0 0 TYP MAX UNITS ns ns ns
t2
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11.6.1 ECP PARALLEL PORT TIMING
Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to FIGURE 30. ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest.
The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in FIGURE 31. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe).
Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in FIGURE 32.
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Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs.
t6 t3 PDATA t1 t2 t5
nSTROBE
t4 BUSY
FIGURE 30 - PARALLEL PORT FIFO TIMING NAME t1 t2 t3 t4 t5 t6 DESCRIPTION DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive (Note 1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 1) MIN 600 600 450 TYP MAX UNITS ns ns ns ns ns ns
500 680 80
Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely.
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t3 nAUTOF t4 PDATA<7:0 t2 t1 t7 nSTROB BUSY t6 t5 t6 t8
FIGURE 31 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed (Notes 1,2) t4 BUSY Deasserted to PDATA Changed (Notes 1,2) t5 nSTROBE Deasserted to Busy Asserted t6 nSTROBE Deasserted to Busy Deasserted t7 BUSY Deasserted to nSTROBE Asserted (Notes 1,2) t8 BUSY Asserted to nSTROBE Deasserted (Note 2) MIN 0 0 80 TYP MAX 60 60 180 UNITS ns ns ns
80 0 0 80 80
180
200 180
ns ns ns ns ns
Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out. Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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t2 PDATA<7:0> t1 t5 nACK t4 nAUTOFD
FIGURE 32 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nAUTOFD Deasserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted (Notes 1,2) t4 nACK Deasserted to nAUTOFD Asserted (Note 2) t5 nAUTOFD Asserted to nACK Asserted t6 nAUTOFD Deasserted to nACK Deasserted MIN 0 0 80 TYP MAX UNITS ns ns ns
t6
t3
t4
200 200
80 0 0
ns ns ns
Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nAUTOFD low. Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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11.7 Infrared Interface Timing Diagrams
DATA
0 t2 t1
1 t2
0
1
0
0
1
1
0
1
1
t1
IRRX n IRRX
Pa rame ter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 1 15kba ud Pul se Wid th at 57.6kba ud Pul se Wid th at 38.4kba ud Pul se Wid th at 19.2kba ud Pu lse Wi dth a t 9.6kba ud Pu lse Wi dth a t 4.8kba ud Pu lse Wi dth a t 2.4kba ud Bit Time at 1 15kba ud Bit Time at 57.6kba ud Bit Time at 38.4kba ud Bit Time at 19.2kba ud Bi t Ti me a t 9.6kba ud Bi t Ti me a t 4.8kba ud Bi t Ti me a t 2.4kba ud
min 1.4 1.4 1.4 1.4 1.4 1.4 1.4
ty p 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 1 04 2 08 4 16
m ax 2.71 3.69 5.53 1 1.07 2 2.13 4 4.27 8 8.55
units s s s s s s s s s s s s s s
No te s: 1. Recei ve Pu lse Detection C ri te ria: A re ceived p ulse is consi dered d etecte d if the receive d p ulse is a mini mum o f 1.41s. 2. IR RX: L5, CRF1 Bit 0 = 1 nIRRX: L5, CRF1 Bi t 0 = 0 (defaul t)
FIGURE 33 - IRDA RECEIVE TIMING
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DAT A
0 t2 t1
1
0
1
0
0
1
1
0
1
1
t2
t1
IRT X n IRT X
Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Widt h at 57. 6kbaud Pulse Widt h at 38. 4kbaud Pulse Widt h at 19. 2kbaud Pulse Widt h at 9. 6kbaud Pulse Widt h at 4. 8kbaud Pulse Widt h at 2. 4kbaud Bit T ime at 115kbaud Bit Tim e at 57. 6kbaud Bit Tim e at 38. 4kbaud Bit Tim e at 19. 2kbaud Bit Tim e at 9. 6kbaud Bit Tim e at 4. 8kbaud Bit Tim e at 2. 4kbaud
mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41
typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416
max 2.71 3.69 5.53 11.07 22.13 44.27 88.55
u nits s s s s s s s s s s s s s s
Notes: 1. IrDA @ 115k i s HPSIR com pati ble. IrDA @ 2400 wi ll al low compat ibilit y with HP95LX and 48SX. 2. IRT X: L5, CRF 1 Bit 1 = 1 (default) nI RT X: L5, CRF1 Bit 1 = 0
FIGURE 34 - IRDA TRANSMIT TIMING
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DA A T 0 t1 IRRX n IRRX 1 t2 0 1 0 0 1 1 0 1 1
t3 M IRRX t5
t4
nM IRRX
t6
Pa ramet er t1 t2 t3 t4 t5 t6 M odu lated Out put Bit T ime Off Bit Time M odu lated Outp ut " On" M odu lated Out put " Off" M odu lated Outp ut " On" M odu lated Out put " Off"
min
typ
max
units s s
0.8 0.8 0.8 0.8
1 1 1 1
1.2 1.2 1.2 1.2
s s s s
Note s: 1 . IRRX: L 5, CRF 1 Bit 0 = 1 n IRRX: L5 , CRF 1 Bit 0 = 0 (de fault) M IRRX, nMI RRX are the mod ulate d ou tpu ts
FIGURE 35 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING
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DATA
0 t1
1 t2
0
1
0
0
1
1
0
1
1
IRTX n IRT X
t3 MIRTX t5 n MIRT X
t4
t6
Pa ramet er t1 t2 t3 t4 t5 t6 M odu lated Out put Bit T ime Off Bit T ime M odu lated Outp ut " On" M odu lated Outp ut " Off" M odu lated Outp ut " On" M odu lated Outp ut " Off"
min
t yp
max
units s s
0.8 0.8 0.8 0.8
1 1 1 1
1.2 1.2 1.2 1.2
s s s s
Note s: 1 . IRT X : L5 , CRF 1 Bit 1 = 1 (def ault) nI RTX: L 5, CRF1 Bit 1 = 0 MIRTX, nM IRTX a re the mod ulate d ou tpu ts
FIGURE 36 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING
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11.8 SMBUS Timing
tLOW SCLK tHD;STA tHD;DAT tSU;STA tSU;STO tR tF tHD;STA
tHIGH
tSU;DAT
SDAT tBUF P S S P
FIGURE 37 - SMBUS TIMING SYMBOL PARAMETER LIMITS MIN MAX 10 100 4.7 UNITS COMMENTS
FSMB TBUF THD:STA
TSU:STA TSU:STO THD:DAT TSU:DAT TTIMEOUT TLOW THIGH TLOW: SEXT TLOW: MEXT TF TR
SMB Operating Frequency Bus free time between Stop and Start Condition Hold time after (Repeated) Start Condition. After this period, the first clock is generated. Repeated Start Condition setup time Stop Condition setup time Data hold time Data setup time Max. Clock low time Clock low period Clock high period Cumulative clock low extend time (slave device) Cumulative clock low extend time (master device) Clock/Data Fall Time Clock/Data Rise Time
kHz
s s
4.0
4.7 4.0 0 250 25 4.7 4.0
s s ns ns ms s s ms
35 50 25 10 300 1000
see note 1 see note 2
ms ns ns
Note 1: A device will timeout when any clock low exceeds this value. Note 2: THIGH Max provides a simple guaranteed method for devices to detect bus idle conditions.
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11.9 X-Bus Timing
Note: The following timing values are based on a 33MHz PCI clock. Timing values will vary with variations in the PCI clock frequency.
11.9.1 TIMING FOR LPC INITIATED I/O CYCLES WITH THE X-BUS
t3
Ax, nXCSx
t1 t2 t5
nXRD
t4
Data
Valid
FIGURE 38 - X-BUS READ TIMING NAME t1 t2 DESCRIPTION nXCS active to nXRD active nXRD active to nXRD inactive MIN 100 A: 180 B: 300 C: 420 D: 540 40 20 0 TYP MAX 190 UNITS ns ns
t3 t4 t5
nXRD inactive to nxCS inactive Data valid to nXRD inactive nXRD inactive to data invalid
ns ns ns
Note: Cases A-D for t2 correspond to the different pulse width options for the X-Bus read strobe. See the X-Bus Selection Configuration Register.
t3
Ax, nXCSx
t1 t2 t5
nXWR
t4
Data
Valid
FIGURE 39 - X-BUS WRITE TIMING
MIN TYP MAX UNITS 100 190 ns ns A: 180 B: 300 C: 420 D: 540 t3 nXWR inactive to nXCS inactive 40 ns t4 Data valid to nXWR active 22 ns t5 nXWR inactive to data invalid 45 ns Note: Cases A-D for t2 correspond to the different pulse width options for the X-Bus write strobe. See the X-Bus Selection Configuration Register.
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NAME t1 t2
DESCRIPTION nXCS active to nXWR active nXWR active to nXWR inactive
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11.9.2 REPRESENTATIVE LPC I/O CYCLE TO X-BUS CYCLE TIMING
X-Bus Read Cycle: LPC I/O Read Cycle - Data from X-Bus Device to Host
PCI_CLK
LFRAME#
LAD[3:0]#
Start C+D
Address
TAR
Sync=0110
Sync 0000
Data
TAR
Ax, nXCSx
nXRD
Data
Valid
FIGURE 40 - X-BUS AND LPC I/O READ CYCLE Note: Minimum read pulse width is shown.
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11.9.3 X-BUS WRITE CYCLE: LPC I/O WRITE CYCLE - DATA FROM HOST TO X-BUS DEVICE
PCI_CLK
LFRAME#
LAD[3:0]#
Start C+D
Address
Data
TAR
Sync=0110
Sync 0000
TAR
Ax, nXCSx
nXWR
Data
Valid
FIGURE 41 - X-BUS AND LPC I/O WRITE CYCLE Note: Minimum write pulse width is shown.
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11.9.4 TIMING FOR SMBUS INITIATED I/O CYCLES WITH THE X-BUS
SMB Data
Command Code
A
Data Byte Data Received
A
P
S
Slave Address
nCS[0, 2, 3] CS1 LCDCS t1 nWr t6 t3 t2 t2
XA[0:3]
Address/Command Address t4 t5 Valid Data Data
XAD0 - XAD7
*Note: Timing Diagram is not to scale.
FIGURE 42 - SMBUS TO X-BUS WRITE CYCLE TIMING FOR LCD AND I/O CYCLES SYMBOL t1 t2 t3 PARAMETER SMB frequency SMB Bit Rate Address Setup Time Address Hold Time Enable Pulse Width MIN 10 10 100 40 A: 180 B: 300 C: 420 D: 540 22 30 140 TYP MAX 100 100 190 A: 215 B: 335 C: 455 D: 575 UNIT kHz sec ns ns ns
(See Note 4) Data valid to nXWr active ns Data Hold Time ns LCDCS Address Setup Time 190 ns (See Note 5) Note: These min/max values satisfy X-Bus write timing and the supported LCD controllers. Note: For the complete SMBus Read/Write protocols see the section on SMBus2 or the SMBus Specification. Note 1: For LCD controllers the total minimum cycle time for LCDCS between latches is 1000ns. The LCDCS latches the data when it transitions from a high to a low level. This should be easily satisfied since the SMBus operates in the micro second range. Note 2: For LCD controllers A0 is the Read/nWrite control bit and A1 is the Data/Control bit. These two bits are the LSB in the command byte. Note 3: The SMBus needs a minimum of 90sec to deliver the Data after the Address is received. The X-Bus needs a minimum of 400nsec to setup the address and control signals before the Data is received. To prevent the SMBus from monopolizing the X-Bus, the chip select and control signals should be made active when both the Address and Data byte are received on the SMBus. (The X-Bus should not begin its cycle for more than a maximum of 1sec before the Data is completely received on the SMBus) Note 4: The default for the Read/Write Enable Pulse Width is 540ns. Note 5: The LCDCS signal will be generated a minimum of 40nsec after nXRD or nXWR transitions to a low state (i.e., LCDCS = nXWR + nXRD with a delay of 40nsec). The Pulse Width of the LCDCS signal will be 40nsec less t4 t5 t6
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than the Enable Pulse Width of the nXRD or nXWR Pulse Width Selection (i.e., Case D: 540nsec-40nsec=500nsec minimum LCDCS Pulse Width)
SMB Data Command Code
A
S
Slave Address/Rd A
Data Byte
A#
P
S
Address Received
nCS[0, 2, 3] CS1 LCDCS nXRd A[0:3] XAD0 - XAD7
t6 t1 t3 t2 t2
Address
t4 t5
valid data
*Note: Timing Diagram is not to scale.
FIGURE 43 - SMBUS TO X-BUS READ CYCLE TIMING FOR LCD AND I/O CYCLES SYMBOL t1 t2 t3 PARAMETER SMB frequency SMB Bit Rate Address Setup Time Address Hold Time Enable Pulse Width MIN 10 10 100 40 A: 180 B: 300 C: 420 D: 540 30 20 140 TYP MAX 100 100 190 A: 215 B: 335 C: 455 D: 575 UNIT kHz sec ns ns ns
(See Note 4) Data Valid to nXRd invalid ns Data Hold Time ns LCD Address Setup Time 190 ns (See Note 5) Note: These min/max values satisfy X-Bus read timing and the supported LCD controllers. Note 1: Total minimum cycle time for LCDCS between latches is 1000ns. The LCDCS latches the data when it transitions from a high to a low level. This should be easily satisfied since the SMBus operates in the micro second range. Note 2: For LCD controllers, A0 is the Read/nWrite control bit and A1 is the Data/Control bit. These two bits are the LSB in the command byte. Note 3: The SMBus needs to wait a minimum of 110sec before it is ready to accept the Data being read. The X-Bus can complete this transaction on the order of 1sec. To prevent the SMBus from holding the X-Bus for an excessive amount of time, the X-Bus should be allowed to complete its transaction, storing the data in a register until the SMBus is ready to take the data. This way the LPC Bus can regain access to the X-Bus. With this implementation, CS1 should go active as soon as the command byte is received, it is determined whether the cycle is a read or write cycle and the SMBus arbitrates rights to the X-Bus. Note 4: The default for the Read/Write Enable Pulse Width is 540ns. Note 5: The LCDCS signal will be generated a minimum of 40nsec after nXRD or nXWR transitions to a low state (i.e., LCDCS = nXWR + nXRD with a delay of 40nsec). The Pulse Width of the LCDCS signal will be 40nsec less than the Enable Pulse Width of the nXRD or nXWR Pulse Width Selection (i.e., Case D: 540nsec-40nsec=500nsec minimum LCDCS Pulse Width) t4 t5 t6
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Note: For Read Cycles initiated by the SMBus, the X-Bus should be accessed as soon as the address (i.e. chip select) is received. For Write Cycles initiated by the SMBus, the X-Bus should be accessed as soon as the Data Byte is received. (i.e. chip select & data). No cycle should begin before it is determined to be a read or a write.
11.10 Timing for Serial IRQ's
PCI_CLK t1 SER_IRQ
FIGURE 44 - SETUP AND HOLD TIME NAME t1 t2 DESCRIPTION SER_IRQ Setup Time to PCI_CLK Rising SER_IRQ Hold Time to PCI_CLK Rising MIN 7 0 TYP MAX UNITS nsec nsec
t2
Data Start TXD1, 2 Data (5-8 Bits) t1 Parity Stop (1-2 Bits)
FIGURE 45 - SERIAL PORT DATA NAME DESCRIPTION MIN TYP MAX UNITS t1 Serial Port Data Bit Time tBR1 nsec Note 1: tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage errors indicated in the "Baud Rate" table in the "Serial Port" section.
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11.11 Keyboard/Mouse Timing
KCLK/ MCLK t1
CLK CLK 1 2 t3 t4
t2 t6
CLK 9
CLK 10
CLK 11 t5
KDAT/ Start Bit MDAT
Bit 0
Bit 7
Parity Bit
Stop Bit
FIGURE 46 - KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING NAME t1 DESCRIPTION Time from DATA transition to falling edge of CLOCK (Receive) Time from rising edge of CLOCK to DATA transition (Receive) Duration of CLOCK inactive (Receive/Send) Duration of CLOCK active (Receive/Send) Time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (Receive) Time from inactive to active CLOCK transition, used to time when the auxiliary device samples DATA (Send) MIN 5 TYP MAX 25 UNITS sec
t2 t3 t4 t5 t6
5 30 30 >0 5
T4-5 50 50 50 25
sec sec sec sec sec
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11.12 Fan Timing
t1 FAN t2
FIGURE 47 - FAN OUTPUT TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 PWM Period (Note 1) 0.021 25.8 msec t2 PWM High Time (Note 2) 0.00033 25.4 msec Note 1: The period is 1/fout,where fout is programmed through the FAN and Fan Control registers. The tolerance on fout is +/- 3%. Note 2: When Bit 0 of the FAN register is 0, then the duty cycle is programmed through Bits[6:1] of these registers. If Bits[6:1] = "000000" then the FAN pin is low. The duty cycle is programmable through Bits[6:1] to be between 1.56% and 98.44%. When Bit 0 is 1, the FAN pin is high.
t1 t2 FAN_TACH
FIGURE 48 - FAN TACHOMTER INPUT TIMING NAME DESCRIPTION t1 Pulse Time (1/2 Revolution Time=30/RPM) t2 Pulse High Time t3 Pulse Low Time Note 1: tTACH is the clock used for the tachometer counter. programmed in the Fan Control register. MIN TYP MAX UNITS 4tTACH1 sec 3tTACH1 sec tTACH sec It is 30.52 * DVSR, where the divisor (DVSR) is
t3
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11.13 Timing for LED Output
t1 t2 LEDx
FIGURE 49 - LED OUTPUT TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 Period 1 2 sec 1 t2 Blink ON Time 0 0.5 sec Note 1: The blink rate is programmed through Bits[1:0] in LEDx register. When Bits[1:0]=00, LED is OFF. Bits[1:0]=01 indicates LED blink at 1Hz rate with a 50% duty cycle (0.5 sec ON, 0.5 sec OFF). Bits[1:0]=10 indicates LED blink at 1/2 Hz rate with a 25% duty cycle (0.5 sec ON, 1.5 sec OFF). When Bits[1:0]=11, LED is ON.
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12 SMSC 128 PIN QFP PACKAGE OUTLINE, 3.9 MM FOOTPRINT.
A A1 A2 D D1 E E1 H L L1 e W R1 R2 ccc
1
MIN ~ 0.05 2.55 23.70 19.90 17.70 13.90 0.09 0.73 ~
0o 0.10 0.13 0.13 ~
NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.88 1.95 0.50 Basic ~ ~ ~ ~ ~
MAX 3.4 0.5 3.05 24.10 20.10 18.10 14.10 0.20 1.03 ~
7o 0.30 ~ 0.30 0.08
REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
Notes: Controlling Unit: millimeter. 2 Tolerance on the position of the leads is 0.04 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated.
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13 APPENDIX - TEST MODES 13.1 Normal Operating Power Supply State
The following table defines the power supply states for normal operation of the chip.
POWER STATE Power Loss/ "Mechanical Off" "Normal Off" On Initial State (Before Battery is installed) Battery dies, but system (VTR) maintains power Battery dies, but system (VTR) maintains power VBAT VTR VCC STATE
ON ON ON OFF OFF OFF
OFF ON ON OFF ON ON
OFF OFF ON OFF OFF ON
valid valid valid valid (Note 1) valid (Note 1) valid (Note 1)
Note: VTR power must be applied to the chip either before or at the same time as VCC. VTR must not power up after VCC. Note: Power is "ON" when Vbat, VTR, or VCC are greater than 2.4 volts. Power is "OFF" when the voltage is less than 0.4 volts. Note 1: When Vbat is turned off (i.e., the battery goes dead), the CMOS in the RTC section that is battery powered will be lost on the next VTR_POR cycle.
The following table defines the invalid power supply states.
POWER STATE Invalid Invalid VBAT ON OFF VTR OFF OFF VCC ON ON STATE invalid invalid
13.2 Test Modes
The XNOR Test chain used in the LPC47X42x is extended to accommodate the extra pins offered by the 128 QFP.
13.2.1 BOARD TEST MODE
Board test mode can be entered as follows: On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low. Exit board test mode as follows: On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high. See the "XNOR-Chain Test Mode" section below for a description of this board test mode.
13.2.2 XNOR-CHAIN TEST MODE
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly and test operations. See Figure 41 below. The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the LPC47S45x pin functions are disconnected from the device pins, which all become input pins except for one output pin at the end of XNOR-Chain. The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to control the device pins and observe the results at the XNOR-Chain output pin. The PCI_RESET# pin is not included in the XNOR-Chain. The XNOR-Chain is output on TXD1 (PIN 88). See the following subsection for more details.
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I/O#1
I/O#2
I/O#3
I/O#n
XNor Out
FIGURE 50 - XNOR-CHAIN TEST STRUCTURE
Introduction The LPC47S45x provides board test capability through the XNOR chain. When the chip is in the XNOR chain test mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to toggle. All pins on the chip are inputs to the XNOR chain, with the exception of the following: 1. 2. 3. 4. 5. 6. VCC (pins 21, 68, & 96), VTR (pins 1, 56, & 125), and Vbat (pin 2). VSS (pins 34, 63, 79, & 106) and AVSS (pin 5) TXD1 (PIN 88). This is the chain output. PCI_RESET# (pin 29 XTAL1 and XTAL2 (pins 3 and 4). XOSEL (pin 124)
To put the chip in the XNOR chain test mode, tie LAD0 (pin 23) and LFRAME# (pin 27) low. Then toggle PCI_RESET# (pin 29) from a low to a high state. Once the chip is put into XNOR chain test mode, LAD0 (pin 23) and LFRAME# (pin 27) become part of the chain. To exit the XNOR chain test mode tie LAD0 (pin 23) or LFRAME# (pin 27) high. Then toggle PCI_RESET# (pin 29) from a low to a high state. A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test mode has been exited, observe the output onTXD1 (PIN 88). Toggling any of the input pins should not cause its state to change. Setup
Warning: Ensure power supply is off during setup.
1. 2. 3. 4. 5. Testing 1. 2. 3. 4. 5.
Connect VSS (pins 34, 63, 79, & 106) to ground. Connect AVSS (pin 5) to analog ground. Connect VCC (pins 21, 68, & 96), VTR (pins 1, 56, & 125), & Vbat (pin 2) to VCC (3.3V). Connect an oscilloscope or voltmeter to output pin TXD1 (PIN 88). All other pins should be tied to ground, except XTAL1 (pin 3), XTAL2 (pin 4), and XOSEL (pin 124).
Turn power on. With LAD0 (pin 23) and nLFRAME (pins 27) low, bring PCI_RESET# (pin 29) high. The chip is now in XNOR chain test mode. At this point, all inputs to the XNOR chain are low. The output on TXD1 (PIN 88) should also be low. Refer to INITIAL CONFIG on Truth Table 1. Bring pin 128 high. The output on TXD1 (PIN 88) should go high. Refer to STEP ONE on Truth Table 1. In descending pin order, bring each input of the XNOR chain high. The output should switch states each time an input is toggled. Continue until all inputs are high. The output on TXD1 (PIN 88) should now be high. Refer to END CONFIG on Truth Table 1. The current state of the chip is now represented by INITIAL CONFIG in Truth Table 2.
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6. 7.
Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all inputs are low. The output on TXD1 (PIN 88) should now be low. Refer to Truth Table 2. To exit test mode, tie LAD0 (pin 23) or LFRAME# (pin 27) high, and toggle PCI_RESET# from a low to a high state.
TRUTH TABLE 1 - Toggling inputs in descending order PIN 128 PIN 127 PIN 126 PIN 123 PIN 122 PIN ... PIN 6 OUTPUT PIN TXD1 (PIN 88) L
INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 ... STEP N END CONFIG
L H H H H H ... H H
L L H H H H ... H H
L L L H H H ... H H
L L L L H H ... H H
L L L L L H ... H H
L L L L L L ... H H
L L L L L L ... L H
H L H L H ... H H
TRUTH TABLE 2 - Toggling inputs in ascending order PIN 6 PIN 7 PIN 8 PIN 9 PIN 10 PIN ... PIN 128 OUTPUT PIN TXD1 (PIN 88) H
INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP N END CONFIG
H L L L L L ... L L
H H L L L L ... L L
H H H L L L ... L L
H H H H L L ... L L
H H H H H L ... L L
H H H H H H ... L L
H H H H H H ... H L
L H L H L ... H L
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